mt76.h 29 KB

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  1. /* SPDX-License-Identifier: ISC */
  2. /*
  3. * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
  4. */
  5. #ifndef __MT76_H
  6. #define __MT76_H
  7. #include <linux/kernel.h>
  8. #include <linux/io.h>
  9. #include <linux/spinlock.h>
  10. #include <linux/skbuff.h>
  11. #include <linux/leds.h>
  12. #include <linux/usb.h>
  13. #include <linux/average.h>
  14. #include <net/mac80211.h>
  15. #include "util.h"
  16. #include "testmode.h"
  17. #define MT_MCU_RING_SIZE 32
  18. #define MT_RX_BUF_SIZE 2048
  19. #define MT_SKB_HEAD_LEN 128
  20. #define MT_MAX_NON_AQL_PKT 16
  21. #define MT_TXQ_FREE_THR 32
  22. struct mt76_dev;
  23. struct mt76_phy;
  24. struct mt76_wcid;
  25. struct mt76_reg_pair {
  26. u32 reg;
  27. u32 value;
  28. };
  29. enum mt76_bus_type {
  30. MT76_BUS_MMIO,
  31. MT76_BUS_USB,
  32. MT76_BUS_SDIO,
  33. };
  34. struct mt76_bus_ops {
  35. u32 (*rr)(struct mt76_dev *dev, u32 offset);
  36. void (*wr)(struct mt76_dev *dev, u32 offset, u32 val);
  37. u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val);
  38. void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data,
  39. int len);
  40. void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data,
  41. int len);
  42. int (*wr_rp)(struct mt76_dev *dev, u32 base,
  43. const struct mt76_reg_pair *rp, int len);
  44. int (*rd_rp)(struct mt76_dev *dev, u32 base,
  45. struct mt76_reg_pair *rp, int len);
  46. enum mt76_bus_type type;
  47. };
  48. #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB)
  49. #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO)
  50. #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO)
  51. enum mt76_txq_id {
  52. MT_TXQ_VO = IEEE80211_AC_VO,
  53. MT_TXQ_VI = IEEE80211_AC_VI,
  54. MT_TXQ_BE = IEEE80211_AC_BE,
  55. MT_TXQ_BK = IEEE80211_AC_BK,
  56. MT_TXQ_PSD,
  57. MT_TXQ_BEACON,
  58. MT_TXQ_CAB,
  59. __MT_TXQ_MAX
  60. };
  61. enum mt76_mcuq_id {
  62. MT_MCUQ_WM,
  63. MT_MCUQ_WA,
  64. MT_MCUQ_FWDL,
  65. __MT_MCUQ_MAX
  66. };
  67. enum mt76_rxq_id {
  68. MT_RXQ_MAIN,
  69. MT_RXQ_MCU,
  70. MT_RXQ_MCU_WA,
  71. MT_RXQ_EXT,
  72. MT_RXQ_EXT_WA,
  73. __MT_RXQ_MAX
  74. };
  75. struct mt76_queue_buf {
  76. dma_addr_t addr;
  77. u16 len;
  78. bool skip_unmap;
  79. };
  80. struct mt76_tx_info {
  81. struct mt76_queue_buf buf[32];
  82. struct sk_buff *skb;
  83. int nbuf;
  84. u32 info;
  85. };
  86. struct mt76_queue_entry {
  87. union {
  88. void *buf;
  89. struct sk_buff *skb;
  90. };
  91. union {
  92. struct mt76_txwi_cache *txwi;
  93. struct urb *urb;
  94. int buf_sz;
  95. };
  96. u32 dma_addr[2];
  97. u16 dma_len[2];
  98. u16 wcid;
  99. bool skip_buf0:1;
  100. bool skip_buf1:1;
  101. bool done:1;
  102. };
  103. struct mt76_queue_regs {
  104. u32 desc_base;
  105. u32 ring_size;
  106. u32 cpu_idx;
  107. u32 dma_idx;
  108. } __packed __aligned(4);
  109. struct mt76_queue {
  110. struct mt76_queue_regs __iomem *regs;
  111. spinlock_t lock;
  112. spinlock_t cleanup_lock;
  113. struct mt76_queue_entry *entry;
  114. struct mt76_desc *desc;
  115. u16 first;
  116. u16 head;
  117. u16 tail;
  118. int ndesc;
  119. int queued;
  120. int buf_size;
  121. bool stopped;
  122. bool blocked;
  123. u8 buf_offset;
  124. u8 hw_idx;
  125. u8 qid;
  126. dma_addr_t desc_dma;
  127. struct sk_buff *rx_head;
  128. struct page_frag_cache rx_page;
  129. };
  130. struct mt76_mcu_ops {
  131. u32 headroom;
  132. u32 tailroom;
  133. int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data,
  134. int len, bool wait_resp);
  135. int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb,
  136. int cmd, int *seq);
  137. int (*mcu_parse_response)(struct mt76_dev *dev, int cmd,
  138. struct sk_buff *skb, int seq);
  139. u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset);
  140. void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val);
  141. int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base,
  142. const struct mt76_reg_pair *rp, int len);
  143. int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base,
  144. struct mt76_reg_pair *rp, int len);
  145. int (*mcu_restart)(struct mt76_dev *dev);
  146. };
  147. struct mt76_queue_ops {
  148. int (*init)(struct mt76_dev *dev);
  149. int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q,
  150. int idx, int n_desc, int bufsize,
  151. u32 ring_base);
  152. int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q,
  153. struct sk_buff *skb, struct mt76_wcid *wcid,
  154. struct ieee80211_sta *sta);
  155. int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q,
  156. struct sk_buff *skb, u32 tx_info);
  157. void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
  158. int *len, u32 *info, bool *more);
  159. void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid);
  160. void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q,
  161. bool flush);
  162. void (*kick)(struct mt76_dev *dev, struct mt76_queue *q);
  163. };
  164. enum mt76_wcid_flags {
  165. MT_WCID_FLAG_CHECK_PS,
  166. MT_WCID_FLAG_PS,
  167. MT_WCID_FLAG_4ADDR,
  168. MT_WCID_FLAG_HDR_TRANS,
  169. };
  170. #define MT76_N_WCIDS 288
  171. /* stored in ieee80211_tx_info::hw_queue */
  172. #define MT_TX_HW_QUEUE_EXT_PHY BIT(3)
  173. DECLARE_EWMA(signal, 10, 8);
  174. #define MT_WCID_TX_INFO_RATE GENMASK(15, 0)
  175. #define MT_WCID_TX_INFO_NSS GENMASK(17, 16)
  176. #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18)
  177. #define MT_WCID_TX_INFO_SET BIT(31)
  178. struct mt76_wcid {
  179. struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS];
  180. atomic_t non_aql_packets;
  181. unsigned long flags;
  182. struct ewma_signal rssi;
  183. int inactive_count;
  184. u16 idx;
  185. u8 hw_key_idx;
  186. u8 hw_key_idx2;
  187. u8 sta:1;
  188. u8 ext_phy:1;
  189. u8 amsdu:1;
  190. u8 rx_check_pn;
  191. u8 rx_key_pn[IEEE80211_NUM_TIDS][6];
  192. u16 cipher;
  193. u32 tx_info;
  194. bool sw_iv;
  195. u8 packet_id;
  196. };
  197. struct mt76_txq {
  198. struct mt76_wcid *wcid;
  199. u16 agg_ssn;
  200. bool send_bar;
  201. bool aggr;
  202. };
  203. struct mt76_txwi_cache {
  204. struct list_head list;
  205. dma_addr_t dma_addr;
  206. struct sk_buff *skb;
  207. };
  208. struct mt76_rx_tid {
  209. struct rcu_head rcu_head;
  210. struct mt76_dev *dev;
  211. spinlock_t lock;
  212. struct delayed_work reorder_work;
  213. u16 head;
  214. u16 size;
  215. u16 nframes;
  216. u8 num;
  217. u8 started:1, stopped:1, timer_pending:1;
  218. struct sk_buff *reorder_buf[];
  219. };
  220. #define MT_TX_CB_DMA_DONE BIT(0)
  221. #define MT_TX_CB_TXS_DONE BIT(1)
  222. #define MT_TX_CB_TXS_FAILED BIT(2)
  223. #define MT_PACKET_ID_MASK GENMASK(6, 0)
  224. #define MT_PACKET_ID_NO_ACK 0
  225. #define MT_PACKET_ID_NO_SKB 1
  226. #define MT_PACKET_ID_FIRST 2
  227. #define MT_PACKET_ID_HAS_RATE BIT(7)
  228. #define MT_TX_STATUS_SKB_TIMEOUT HZ
  229. struct mt76_tx_cb {
  230. unsigned long jiffies;
  231. u16 wcid;
  232. u8 pktid;
  233. u8 flags;
  234. };
  235. enum {
  236. MT76_STATE_INITIALIZED,
  237. MT76_STATE_RUNNING,
  238. MT76_STATE_MCU_RUNNING,
  239. MT76_SCANNING,
  240. MT76_HW_SCANNING,
  241. MT76_HW_SCHED_SCANNING,
  242. MT76_RESTART,
  243. MT76_RESET,
  244. MT76_MCU_RESET,
  245. MT76_REMOVED,
  246. MT76_READING_STATS,
  247. MT76_STATE_POWER_OFF,
  248. MT76_STATE_SUSPEND,
  249. MT76_STATE_ROC,
  250. MT76_STATE_PM,
  251. };
  252. struct mt76_hw_cap {
  253. bool has_2ghz;
  254. bool has_5ghz;
  255. };
  256. #define MT_DRV_TXWI_NO_FREE BIT(0)
  257. #define MT_DRV_TX_ALIGNED4_SKBS BIT(1)
  258. #define MT_DRV_SW_RX_AIRTIME BIT(2)
  259. #define MT_DRV_RX_DMA_HDR BIT(3)
  260. #define MT_DRV_HW_MGMT_TXQ BIT(4)
  261. #define MT_DRV_AMSDU_OFFLOAD BIT(5)
  262. struct mt76_driver_ops {
  263. u32 drv_flags;
  264. u32 survey_flags;
  265. u16 txwi_size;
  266. u8 mcs_rates;
  267. void (*update_survey)(struct mt76_dev *dev);
  268. int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr,
  269. enum mt76_txq_id qid, struct mt76_wcid *wcid,
  270. struct ieee80211_sta *sta,
  271. struct mt76_tx_info *tx_info);
  272. void (*tx_complete_skb)(struct mt76_dev *dev,
  273. struct mt76_queue_entry *e);
  274. bool (*tx_status_data)(struct mt76_dev *dev, u8 *update);
  275. void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q,
  276. struct sk_buff *skb);
  277. void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q);
  278. void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta,
  279. bool ps);
  280. int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif,
  281. struct ieee80211_sta *sta);
  282. void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif,
  283. struct ieee80211_sta *sta);
  284. void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif,
  285. struct ieee80211_sta *sta);
  286. };
  287. struct mt76_channel_state {
  288. u64 cc_active;
  289. u64 cc_busy;
  290. u64 cc_rx;
  291. u64 cc_bss_rx;
  292. u64 cc_tx;
  293. s8 noise;
  294. };
  295. struct mt76_sband {
  296. struct ieee80211_supported_band sband;
  297. struct mt76_channel_state *chan;
  298. };
  299. struct mt76_rate_power {
  300. union {
  301. struct {
  302. s8 cck[4];
  303. s8 ofdm[8];
  304. s8 stbc[10];
  305. s8 ht[16];
  306. s8 vht[10];
  307. };
  308. s8 all[48];
  309. };
  310. };
  311. /* addr req mask */
  312. #define MT_VEND_TYPE_EEPROM BIT(31)
  313. #define MT_VEND_TYPE_CFG BIT(30)
  314. #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG)
  315. #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n))
  316. enum mt_vendor_req {
  317. MT_VEND_DEV_MODE = 0x1,
  318. MT_VEND_WRITE = 0x2,
  319. MT_VEND_POWER_ON = 0x4,
  320. MT_VEND_MULTI_WRITE = 0x6,
  321. MT_VEND_MULTI_READ = 0x7,
  322. MT_VEND_READ_EEPROM = 0x9,
  323. MT_VEND_WRITE_FCE = 0x42,
  324. MT_VEND_WRITE_CFG = 0x46,
  325. MT_VEND_READ_CFG = 0x47,
  326. MT_VEND_READ_EXT = 0x63,
  327. MT_VEND_WRITE_EXT = 0x66,
  328. MT_VEND_FEATURE_SET = 0x91,
  329. };
  330. enum mt76u_in_ep {
  331. MT_EP_IN_PKT_RX,
  332. MT_EP_IN_CMD_RESP,
  333. __MT_EP_IN_MAX,
  334. };
  335. enum mt76u_out_ep {
  336. MT_EP_OUT_INBAND_CMD,
  337. MT_EP_OUT_AC_BE,
  338. MT_EP_OUT_AC_BK,
  339. MT_EP_OUT_AC_VI,
  340. MT_EP_OUT_AC_VO,
  341. MT_EP_OUT_HCCA,
  342. __MT_EP_OUT_MAX,
  343. };
  344. struct mt76_mcu {
  345. struct mutex mutex;
  346. u32 msg_seq;
  347. int timeout;
  348. struct sk_buff_head res_q;
  349. wait_queue_head_t wait;
  350. };
  351. #define MT_TX_SG_MAX_SIZE 8
  352. #define MT_RX_SG_MAX_SIZE 4
  353. #define MT_NUM_TX_ENTRIES 256
  354. #define MT_NUM_RX_ENTRIES 128
  355. #define MCU_RESP_URB_SIZE 1024
  356. struct mt76_usb {
  357. struct mutex usb_ctrl_mtx;
  358. u8 *data;
  359. u16 data_len;
  360. struct mt76_worker status_worker;
  361. struct mt76_worker rx_worker;
  362. struct work_struct stat_work;
  363. u8 out_ep[__MT_EP_OUT_MAX];
  364. u8 in_ep[__MT_EP_IN_MAX];
  365. bool sg_en;
  366. struct mt76u_mcu {
  367. u8 *data;
  368. /* multiple reads */
  369. struct mt76_reg_pair *rp;
  370. int rp_len;
  371. u32 base;
  372. bool burst;
  373. } mcu;
  374. };
  375. #define MT76S_XMIT_BUF_SZ (16 * PAGE_SIZE)
  376. struct mt76_sdio {
  377. struct mt76_worker txrx_worker;
  378. struct mt76_worker status_worker;
  379. struct mt76_worker net_worker;
  380. struct work_struct stat_work;
  381. u8 *xmit_buf[IEEE80211_NUM_ACS + 2];
  382. struct sdio_func *func;
  383. void *intr_data;
  384. struct {
  385. int pse_data_quota;
  386. int ple_data_quota;
  387. int pse_mcu_quota;
  388. int deficit;
  389. } sched;
  390. };
  391. struct mt76_mmio {
  392. void __iomem *regs;
  393. spinlock_t irq_lock;
  394. u32 irqmask;
  395. };
  396. struct mt76_rx_status {
  397. union {
  398. struct mt76_wcid *wcid;
  399. u16 wcid_idx;
  400. };
  401. unsigned long reorder_time;
  402. u32 ampdu_ref;
  403. u8 iv[6];
  404. u8 ext_phy:1;
  405. u8 aggr:1;
  406. u8 qos_ctl;
  407. u16 seqno;
  408. u16 freq;
  409. u32 flag;
  410. u8 enc_flags;
  411. u8 encoding:2, bw:3, he_ru:3;
  412. u8 he_gi:2, he_dcm:1;
  413. u8 amsdu:1, first_amsdu:1, last_amsdu:1;
  414. u8 rate_idx;
  415. u8 nss;
  416. u8 band;
  417. s8 signal;
  418. u8 chains;
  419. s8 chain_signal[IEEE80211_MAX_CHAINS];
  420. };
  421. struct mt76_testmode_ops {
  422. int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state);
  423. int (*set_params)(struct mt76_phy *phy, struct nlattr **tb,
  424. enum mt76_testmode_state new_state);
  425. int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg);
  426. };
  427. struct mt76_testmode_data {
  428. enum mt76_testmode_state state;
  429. u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)];
  430. struct sk_buff *tx_skb;
  431. u32 tx_count;
  432. u16 tx_msdu_len;
  433. u8 tx_rate_mode;
  434. u8 tx_rate_idx;
  435. u8 tx_rate_nss;
  436. u8 tx_rate_sgi;
  437. u8 tx_rate_ldpc;
  438. u8 tx_rate_stbc;
  439. u8 tx_ltf;
  440. u8 tx_antenna_mask;
  441. u8 tx_spe_idx;
  442. u8 tx_duty_cycle;
  443. u32 tx_time;
  444. u32 tx_ipg;
  445. u32 freq_offset;
  446. u8 tx_power[4];
  447. u8 tx_power_control;
  448. u32 tx_pending;
  449. u32 tx_queued;
  450. u16 tx_queued_limit;
  451. u32 tx_done;
  452. struct {
  453. u64 packets[__MT_RXQ_MAX];
  454. u64 fcs_error[__MT_RXQ_MAX];
  455. } rx_stats;
  456. };
  457. struct mt76_vif {
  458. u8 idx;
  459. u8 omac_idx;
  460. u8 band_idx;
  461. u8 wmm_idx;
  462. u8 scan_seq_num;
  463. };
  464. struct mt76_phy {
  465. struct ieee80211_hw *hw;
  466. struct mt76_dev *dev;
  467. void *priv;
  468. unsigned long state;
  469. struct mt76_queue *q_tx[__MT_TXQ_MAX];
  470. struct cfg80211_chan_def chandef;
  471. struct ieee80211_channel *main_chan;
  472. struct mt76_channel_state *chan_state;
  473. ktime_t survey_time;
  474. struct mt76_hw_cap cap;
  475. struct mt76_sband sband_2g;
  476. struct mt76_sband sband_5g;
  477. u8 macaddr[ETH_ALEN];
  478. int txpower_cur;
  479. u8 antenna_mask;
  480. u16 chainmask;
  481. #ifdef CONFIG_NL80211_TESTMODE
  482. struct mt76_testmode_data test;
  483. #endif
  484. struct delayed_work mac_work;
  485. u8 mac_work_count;
  486. };
  487. struct mt76_dev {
  488. struct mt76_phy phy; /* must be first */
  489. struct mt76_phy *phy2;
  490. struct ieee80211_hw *hw;
  491. spinlock_t lock;
  492. spinlock_t cc_lock;
  493. u32 cur_cc_bss_rx;
  494. struct mt76_rx_status rx_ampdu_status;
  495. u32 rx_ampdu_len;
  496. u32 rx_ampdu_ref;
  497. struct mutex mutex;
  498. const struct mt76_bus_ops *bus;
  499. const struct mt76_driver_ops *drv;
  500. const struct mt76_mcu_ops *mcu_ops;
  501. struct device *dev;
  502. struct mt76_mcu mcu;
  503. struct net_device napi_dev;
  504. spinlock_t rx_lock;
  505. struct napi_struct napi[__MT_RXQ_MAX];
  506. struct sk_buff_head rx_skb[__MT_RXQ_MAX];
  507. struct {
  508. struct sk_buff *head;
  509. struct sk_buff **tail;
  510. u16 seqno;
  511. } rx_amsdu[__MT_RXQ_MAX];
  512. struct list_head txwi_cache;
  513. struct mt76_queue *q_mcu[__MT_MCUQ_MAX];
  514. struct mt76_queue q_rx[__MT_RXQ_MAX];
  515. const struct mt76_queue_ops *queue_ops;
  516. int tx_dma_idx[4];
  517. struct mt76_worker tx_worker;
  518. struct napi_struct tx_napi;
  519. wait_queue_head_t tx_wait;
  520. struct sk_buff_head status_list;
  521. u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)];
  522. u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)];
  523. u32 vif_mask;
  524. struct mt76_wcid global_wcid;
  525. struct mt76_wcid __rcu *wcid[MT76_N_WCIDS];
  526. u32 rev;
  527. u32 aggr_stats[32];
  528. struct tasklet_struct pre_tbtt_tasklet;
  529. int beacon_int;
  530. u8 beacon_mask;
  531. struct debugfs_blob_wrapper eeprom;
  532. struct debugfs_blob_wrapper otp;
  533. struct mt76_rate_power rate_power;
  534. char alpha2[3];
  535. enum nl80211_dfs_regions region;
  536. u32 debugfs_reg;
  537. struct led_classdev led_cdev;
  538. char led_name[32];
  539. bool led_al;
  540. u8 led_pin;
  541. u8 csa_complete;
  542. u32 rxfilter;
  543. #ifdef CONFIG_NL80211_TESTMODE
  544. const struct mt76_testmode_ops *test_ops;
  545. struct {
  546. const char *name;
  547. u32 offset;
  548. } test_mtd;
  549. #endif
  550. struct workqueue_struct *wq;
  551. union {
  552. struct mt76_mmio mmio;
  553. struct mt76_usb usb;
  554. struct mt76_sdio sdio;
  555. };
  556. };
  557. struct mt76_power_limits {
  558. s8 cck[4];
  559. s8 ofdm[8];
  560. s8 mcs[4][10];
  561. s8 ru[7][12];
  562. };
  563. enum mt76_phy_type {
  564. MT_PHY_TYPE_CCK,
  565. MT_PHY_TYPE_OFDM,
  566. MT_PHY_TYPE_HT,
  567. MT_PHY_TYPE_HT_GF,
  568. MT_PHY_TYPE_VHT,
  569. MT_PHY_TYPE_HE_SU = 8,
  570. MT_PHY_TYPE_HE_EXT_SU,
  571. MT_PHY_TYPE_HE_TB,
  572. MT_PHY_TYPE_HE_MU,
  573. };
  574. #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__)
  575. #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__)
  576. #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__)
  577. #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__)
  578. #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__)
  579. #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val)
  580. #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0)
  581. #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__)
  582. #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__)
  583. #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__)
  584. #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__)
  585. #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__)
  586. #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__)
  587. #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__)
  588. #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76))
  589. #define __mt76_mcu_restart(dev, ...) (dev)->mcu_ops->mcu_restart((dev))
  590. #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val)
  591. #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0)
  592. #define mt76_get_field(_dev, _reg, _field) \
  593. FIELD_GET(_field, mt76_rr(dev, _reg))
  594. #define mt76_rmw_field(_dev, _reg, _field, _val) \
  595. mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
  596. #define __mt76_rmw_field(_dev, _reg, _field, _val) \
  597. __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
  598. #define mt76_hw(dev) (dev)->mphy.hw
  599. static inline struct ieee80211_hw *
  600. mt76_wcid_hw(struct mt76_dev *dev, u16 wcid)
  601. {
  602. if (wcid <= MT76_N_WCIDS &&
  603. mt76_wcid_mask_test(dev->wcid_phy_mask, wcid))
  604. return dev->phy2->hw;
  605. return dev->phy.hw;
  606. }
  607. bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
  608. int timeout);
  609. #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__)
  610. bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
  611. int timeout);
  612. #define mt76_poll_msec(dev, ...) __mt76_poll_msec(&((dev)->mt76), __VA_ARGS__)
  613. void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs);
  614. void mt76_pci_disable_aspm(struct pci_dev *pdev);
  615. static inline u16 mt76_chip(struct mt76_dev *dev)
  616. {
  617. return dev->rev >> 16;
  618. }
  619. static inline u16 mt76_rev(struct mt76_dev *dev)
  620. {
  621. return dev->rev & 0xffff;
  622. }
  623. #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76))
  624. #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76))
  625. #define mt76_init_queues(dev) (dev)->mt76.queue_ops->init(&((dev)->mt76))
  626. #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__)
  627. #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__)
  628. #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__)
  629. #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__)
  630. #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__)
  631. #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__)
  632. #define mt76_for_each_q_rx(dev, i) \
  633. for (i = 0; i < ARRAY_SIZE((dev)->q_rx) && \
  634. (dev)->q_rx[i].ndesc; i++)
  635. struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size,
  636. const struct ieee80211_ops *ops,
  637. const struct mt76_driver_ops *drv_ops);
  638. int mt76_register_device(struct mt76_dev *dev, bool vht,
  639. struct ieee80211_rate *rates, int n_rates);
  640. void mt76_unregister_device(struct mt76_dev *dev);
  641. void mt76_free_device(struct mt76_dev *dev);
  642. void mt76_unregister_phy(struct mt76_phy *phy);
  643. struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size,
  644. const struct ieee80211_ops *ops);
  645. int mt76_register_phy(struct mt76_phy *phy, bool vht,
  646. struct ieee80211_rate *rates, int n_rates);
  647. struct dentry *mt76_register_debugfs(struct mt76_dev *dev);
  648. int mt76_queues_read(struct seq_file *s, void *data);
  649. void mt76_seq_puts_array(struct seq_file *file, const char *str,
  650. s8 *val, int len);
  651. int mt76_eeprom_init(struct mt76_dev *dev, int len);
  652. void mt76_eeprom_override(struct mt76_phy *phy);
  653. struct mt76_queue *
  654. mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc,
  655. int ring_base);
  656. static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx,
  657. int n_desc, int ring_base)
  658. {
  659. struct mt76_queue *q;
  660. q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base);
  661. if (IS_ERR(q))
  662. return PTR_ERR(q);
  663. q->qid = qid;
  664. phy->q_tx[qid] = q;
  665. return 0;
  666. }
  667. static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx,
  668. int n_desc, int ring_base)
  669. {
  670. struct mt76_queue *q;
  671. q = mt76_init_queue(dev, qid, idx, n_desc, ring_base);
  672. if (IS_ERR(q))
  673. return PTR_ERR(q);
  674. q->qid = __MT_TXQ_MAX + qid;
  675. dev->q_mcu[qid] = q;
  676. return 0;
  677. }
  678. static inline struct mt76_phy *
  679. mt76_dev_phy(struct mt76_dev *dev, bool phy_ext)
  680. {
  681. if (phy_ext && dev->phy2)
  682. return dev->phy2;
  683. return &dev->phy;
  684. }
  685. static inline struct ieee80211_hw *
  686. mt76_phy_hw(struct mt76_dev *dev, bool phy_ext)
  687. {
  688. return mt76_dev_phy(dev, phy_ext)->hw;
  689. }
  690. static inline u8 *
  691. mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t)
  692. {
  693. return (u8 *)t - dev->drv->txwi_size;
  694. }
  695. /* increment with wrap-around */
  696. static inline int mt76_incr(int val, int size)
  697. {
  698. return (val + 1) & (size - 1);
  699. }
  700. /* decrement with wrap-around */
  701. static inline int mt76_decr(int val, int size)
  702. {
  703. return (val - 1) & (size - 1);
  704. }
  705. u8 mt76_ac_to_hwq(u8 ac);
  706. static inline struct ieee80211_txq *
  707. mtxq_to_txq(struct mt76_txq *mtxq)
  708. {
  709. void *ptr = mtxq;
  710. return container_of(ptr, struct ieee80211_txq, drv_priv);
  711. }
  712. static inline struct ieee80211_sta *
  713. wcid_to_sta(struct mt76_wcid *wcid)
  714. {
  715. void *ptr = wcid;
  716. if (!wcid || !wcid->sta)
  717. return NULL;
  718. return container_of(ptr, struct ieee80211_sta, drv_priv);
  719. }
  720. static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb)
  721. {
  722. BUILD_BUG_ON(sizeof(struct mt76_tx_cb) >
  723. sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data));
  724. return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data);
  725. }
  726. static inline void *mt76_skb_get_hdr(struct sk_buff *skb)
  727. {
  728. struct mt76_rx_status mstat;
  729. u8 *data = skb->data;
  730. /* Alignment concerns */
  731. BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4);
  732. BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4);
  733. mstat = *((struct mt76_rx_status *)skb->cb);
  734. if (mstat.flag & RX_FLAG_RADIOTAP_HE)
  735. data += sizeof(struct ieee80211_radiotap_he);
  736. if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU)
  737. data += sizeof(struct ieee80211_radiotap_he_mu);
  738. return data;
  739. }
  740. static inline void mt76_insert_hdr_pad(struct sk_buff *skb)
  741. {
  742. int len = ieee80211_get_hdrlen_from_skb(skb);
  743. if (len % 4 == 0)
  744. return;
  745. skb_push(skb, 2);
  746. memmove(skb->data, skb->data + 2, len);
  747. skb->data[len] = 0;
  748. skb->data[len + 1] = 0;
  749. }
  750. static inline bool mt76_is_skb_pktid(u8 pktid)
  751. {
  752. if (pktid & MT_PACKET_ID_HAS_RATE)
  753. return false;
  754. return pktid >= MT_PACKET_ID_FIRST;
  755. }
  756. static inline u8 mt76_tx_power_nss_delta(u8 nss)
  757. {
  758. static const u8 nss_delta[4] = { 0, 6, 9, 12 };
  759. return nss_delta[nss - 1];
  760. }
  761. static inline bool mt76_testmode_enabled(struct mt76_phy *phy)
  762. {
  763. #ifdef CONFIG_NL80211_TESTMODE
  764. return phy->test.state != MT76_TM_STATE_OFF;
  765. #else
  766. return false;
  767. #endif
  768. }
  769. static inline bool mt76_is_testmode_skb(struct mt76_dev *dev,
  770. struct sk_buff *skb,
  771. struct ieee80211_hw **hw)
  772. {
  773. #ifdef CONFIG_NL80211_TESTMODE
  774. if (skb == dev->phy.test.tx_skb)
  775. *hw = dev->phy.hw;
  776. else if (dev->phy2 && skb == dev->phy2->test.tx_skb)
  777. *hw = dev->phy2->hw;
  778. else
  779. return false;
  780. return true;
  781. #else
  782. return false;
  783. #endif
  784. }
  785. void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb);
  786. void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta,
  787. struct mt76_wcid *wcid, struct sk_buff *skb);
  788. void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq);
  789. void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta,
  790. bool send_bar);
  791. void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb);
  792. void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid);
  793. void mt76_txq_schedule_all(struct mt76_phy *phy);
  794. void mt76_tx_worker(struct mt76_worker *w);
  795. void mt76_release_buffered_frames(struct ieee80211_hw *hw,
  796. struct ieee80211_sta *sta,
  797. u16 tids, int nframes,
  798. enum ieee80211_frame_release_type reason,
  799. bool more_data);
  800. bool mt76_has_tx_pending(struct mt76_phy *phy);
  801. void mt76_set_channel(struct mt76_phy *phy);
  802. void mt76_update_survey(struct mt76_dev *dev);
  803. void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time);
  804. int mt76_get_survey(struct ieee80211_hw *hw, int idx,
  805. struct survey_info *survey);
  806. void mt76_set_stream_caps(struct mt76_phy *phy, bool vht);
  807. int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid,
  808. u16 ssn, u16 size);
  809. void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid);
  810. void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid,
  811. struct ieee80211_key_conf *key);
  812. void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list)
  813. __acquires(&dev->status_list.lock);
  814. void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list)
  815. __releases(&dev->status_list.lock);
  816. int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid,
  817. struct sk_buff *skb);
  818. struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev,
  819. struct mt76_wcid *wcid, int pktid,
  820. struct sk_buff_head *list);
  821. void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb,
  822. struct sk_buff_head *list);
  823. void mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb);
  824. void mt76_tx_status_check(struct mt76_dev *dev, struct mt76_wcid *wcid,
  825. bool flush);
  826. int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  827. struct ieee80211_sta *sta,
  828. enum ieee80211_sta_state old_state,
  829. enum ieee80211_sta_state new_state);
  830. void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif,
  831. struct ieee80211_sta *sta);
  832. void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  833. struct ieee80211_sta *sta);
  834. int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy);
  835. int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  836. int *dbm);
  837. void mt76_csa_check(struct mt76_dev *dev);
  838. void mt76_csa_finish(struct mt76_dev *dev);
  839. int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant);
  840. int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set);
  841. void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id);
  842. int mt76_get_rate(struct mt76_dev *dev,
  843. struct ieee80211_supported_band *sband,
  844. int idx, bool cck);
  845. void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  846. const u8 *mac);
  847. void mt76_sw_scan_complete(struct ieee80211_hw *hw,
  848. struct ieee80211_vif *vif);
  849. int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  850. void *data, int len);
  851. int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb,
  852. struct netlink_callback *cb, void *data, int len);
  853. int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state);
  854. static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable)
  855. {
  856. #ifdef CONFIG_NL80211_TESTMODE
  857. enum mt76_testmode_state state = MT76_TM_STATE_IDLE;
  858. if (disable || phy->test.state == MT76_TM_STATE_OFF)
  859. state = MT76_TM_STATE_OFF;
  860. mt76_testmode_set_state(phy, state);
  861. #endif
  862. }
  863. /* internal */
  864. static inline struct ieee80211_hw *
  865. mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb)
  866. {
  867. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  868. struct ieee80211_hw *hw = dev->phy.hw;
  869. if ((info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY) && dev->phy2)
  870. hw = dev->phy2->hw;
  871. info->hw_queue &= ~MT_TX_HW_QUEUE_EXT_PHY;
  872. return hw;
  873. }
  874. void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
  875. void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames,
  876. struct napi_struct *napi);
  877. void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
  878. struct napi_struct *napi);
  879. void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames);
  880. void mt76_testmode_tx_pending(struct mt76_phy *phy);
  881. void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q,
  882. struct mt76_queue_entry *e);
  883. /* usb */
  884. static inline bool mt76u_urb_error(struct urb *urb)
  885. {
  886. return urb->status &&
  887. urb->status != -ECONNRESET &&
  888. urb->status != -ESHUTDOWN &&
  889. urb->status != -ENOENT;
  890. }
  891. /* Map hardware queues to usb endpoints */
  892. static inline u8 q2ep(u8 qid)
  893. {
  894. /* TODO: take management packets to queue 5 */
  895. return qid + 1;
  896. }
  897. static inline int
  898. mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len,
  899. int timeout, int ep)
  900. {
  901. struct usb_interface *uintf = to_usb_interface(dev->dev);
  902. struct usb_device *udev = interface_to_usbdev(uintf);
  903. struct mt76_usb *usb = &dev->usb;
  904. unsigned int pipe;
  905. if (actual_len)
  906. pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]);
  907. else
  908. pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]);
  909. return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout);
  910. }
  911. int mt76_skb_adjust_pad(struct sk_buff *skb, int pad);
  912. int mt76u_vendor_request(struct mt76_dev *dev, u8 req,
  913. u8 req_type, u16 val, u16 offset,
  914. void *buf, size_t len);
  915. void mt76u_single_wr(struct mt76_dev *dev, const u8 req,
  916. const u16 offset, const u32 val);
  917. int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf,
  918. bool ext);
  919. int mt76u_alloc_mcu_queue(struct mt76_dev *dev);
  920. int mt76u_alloc_queues(struct mt76_dev *dev);
  921. void mt76u_stop_tx(struct mt76_dev *dev);
  922. void mt76u_stop_rx(struct mt76_dev *dev);
  923. int mt76u_resume_rx(struct mt76_dev *dev);
  924. void mt76u_queues_deinit(struct mt76_dev *dev);
  925. int mt76s_init(struct mt76_dev *dev, struct sdio_func *func,
  926. const struct mt76_bus_ops *bus_ops);
  927. int mt76s_alloc_queues(struct mt76_dev *dev);
  928. void mt76s_deinit(struct mt76_dev *dev);
  929. struct sk_buff *
  930. mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data,
  931. int data_len);
  932. void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb);
  933. struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev,
  934. unsigned long expires);
  935. int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data,
  936. int len, bool wait_resp, struct sk_buff **ret);
  937. int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb,
  938. int cmd, bool wait_resp, struct sk_buff **ret);
  939. int mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data,
  940. int len);
  941. static inline int
  942. mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len,
  943. bool wait_resp)
  944. {
  945. return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL);
  946. }
  947. static inline int
  948. mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd,
  949. bool wait_resp)
  950. {
  951. return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL);
  952. }
  953. void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set);
  954. s8 mt76_get_rate_power_limits(struct mt76_phy *phy,
  955. struct ieee80211_channel *chan,
  956. struct mt76_power_limits *dest,
  957. s8 target_power);
  958. #endif