mt76.h 31 KB

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  1. /* SPDX-License-Identifier: ISC */
  2. /*
  3. * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
  4. */
  5. #ifndef __MT76_H
  6. #define __MT76_H
  7. #include <linux/kernel.h>
  8. #include <linux/io.h>
  9. #include <linux/spinlock.h>
  10. #include <linux/skbuff.h>
  11. #include <linux/leds.h>
  12. #include <linux/usb.h>
  13. #include <linux/average.h>
  14. #include <net/mac80211.h>
  15. #include "util.h"
  16. #include "testmode.h"
  17. #define MT_MCU_RING_SIZE 32
  18. #define MT_RX_BUF_SIZE 2048
  19. #define MT_SKB_HEAD_LEN 128
  20. #define MT_MAX_NON_AQL_PKT 16
  21. #define MT_TXQ_FREE_THR 32
  22. #define MT76_TOKEN_FREE_THR 64
  23. struct mt76_dev;
  24. struct mt76_phy;
  25. struct mt76_wcid;
  26. struct mt76_reg_pair {
  27. u32 reg;
  28. u32 value;
  29. };
  30. enum mt76_bus_type {
  31. MT76_BUS_MMIO,
  32. MT76_BUS_USB,
  33. MT76_BUS_SDIO,
  34. };
  35. struct mt76_bus_ops {
  36. u32 (*rr)(struct mt76_dev *dev, u32 offset);
  37. void (*wr)(struct mt76_dev *dev, u32 offset, u32 val);
  38. u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val);
  39. void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data,
  40. int len);
  41. void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data,
  42. int len);
  43. int (*wr_rp)(struct mt76_dev *dev, u32 base,
  44. const struct mt76_reg_pair *rp, int len);
  45. int (*rd_rp)(struct mt76_dev *dev, u32 base,
  46. struct mt76_reg_pair *rp, int len);
  47. enum mt76_bus_type type;
  48. };
  49. #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB)
  50. #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO)
  51. #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO)
  52. enum mt76_txq_id {
  53. MT_TXQ_VO = IEEE80211_AC_VO,
  54. MT_TXQ_VI = IEEE80211_AC_VI,
  55. MT_TXQ_BE = IEEE80211_AC_BE,
  56. MT_TXQ_BK = IEEE80211_AC_BK,
  57. MT_TXQ_PSD,
  58. MT_TXQ_BEACON,
  59. MT_TXQ_CAB,
  60. __MT_TXQ_MAX
  61. };
  62. enum mt76_mcuq_id {
  63. MT_MCUQ_WM,
  64. MT_MCUQ_WA,
  65. MT_MCUQ_FWDL,
  66. __MT_MCUQ_MAX
  67. };
  68. enum mt76_rxq_id {
  69. MT_RXQ_MAIN,
  70. MT_RXQ_MCU,
  71. MT_RXQ_MCU_WA,
  72. MT_RXQ_EXT,
  73. MT_RXQ_EXT_WA,
  74. __MT_RXQ_MAX
  75. };
  76. struct mt76_queue_buf {
  77. dma_addr_t addr;
  78. u16 len;
  79. bool skip_unmap;
  80. };
  81. struct mt76_tx_info {
  82. struct mt76_queue_buf buf[32];
  83. struct sk_buff *skb;
  84. int nbuf;
  85. u32 info;
  86. };
  87. struct mt76_queue_entry {
  88. union {
  89. void *buf;
  90. struct sk_buff *skb;
  91. };
  92. union {
  93. struct mt76_txwi_cache *txwi;
  94. struct urb *urb;
  95. int buf_sz;
  96. };
  97. u32 dma_addr[2];
  98. u16 dma_len[2];
  99. u16 wcid;
  100. bool skip_buf0:1;
  101. bool skip_buf1:1;
  102. bool done:1;
  103. };
  104. struct mt76_queue_regs {
  105. u32 desc_base;
  106. u32 ring_size;
  107. u32 cpu_idx;
  108. u32 dma_idx;
  109. } __packed __aligned(4);
  110. struct mt76_queue {
  111. struct mt76_queue_regs __iomem *regs;
  112. spinlock_t lock;
  113. spinlock_t cleanup_lock;
  114. struct mt76_queue_entry *entry;
  115. struct mt76_desc *desc;
  116. u16 first;
  117. u16 head;
  118. u16 tail;
  119. int ndesc;
  120. int queued;
  121. int buf_size;
  122. bool stopped;
  123. bool blocked;
  124. u8 buf_offset;
  125. u8 hw_idx;
  126. u8 qid;
  127. dma_addr_t desc_dma;
  128. struct sk_buff *rx_head;
  129. struct page_frag_cache rx_page;
  130. };
  131. struct mt76_mcu_ops {
  132. u32 headroom;
  133. u32 tailroom;
  134. int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data,
  135. int len, bool wait_resp);
  136. int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb,
  137. int cmd, int *seq);
  138. int (*mcu_parse_response)(struct mt76_dev *dev, int cmd,
  139. struct sk_buff *skb, int seq);
  140. u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset);
  141. void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val);
  142. int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base,
  143. const struct mt76_reg_pair *rp, int len);
  144. int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base,
  145. struct mt76_reg_pair *rp, int len);
  146. int (*mcu_restart)(struct mt76_dev *dev);
  147. };
  148. struct mt76_queue_ops {
  149. int (*init)(struct mt76_dev *dev,
  150. int (*poll)(struct napi_struct *napi, int budget));
  151. int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q,
  152. int idx, int n_desc, int bufsize,
  153. u32 ring_base);
  154. int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q,
  155. struct sk_buff *skb, struct mt76_wcid *wcid,
  156. struct ieee80211_sta *sta);
  157. int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q,
  158. struct sk_buff *skb, u32 tx_info);
  159. void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
  160. int *len, u32 *info, bool *more);
  161. void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid);
  162. void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q,
  163. bool flush);
  164. void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q);
  165. void (*kick)(struct mt76_dev *dev, struct mt76_queue *q);
  166. void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q);
  167. };
  168. enum mt76_wcid_flags {
  169. MT_WCID_FLAG_CHECK_PS,
  170. MT_WCID_FLAG_PS,
  171. MT_WCID_FLAG_4ADDR,
  172. MT_WCID_FLAG_HDR_TRANS,
  173. };
  174. #define MT76_N_WCIDS 288
  175. /* stored in ieee80211_tx_info::hw_queue */
  176. #define MT_TX_HW_QUEUE_EXT_PHY BIT(3)
  177. DECLARE_EWMA(signal, 10, 8);
  178. #define MT_WCID_TX_INFO_RATE GENMASK(15, 0)
  179. #define MT_WCID_TX_INFO_NSS GENMASK(17, 16)
  180. #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18)
  181. #define MT_WCID_TX_INFO_SET BIT(31)
  182. struct mt76_wcid {
  183. struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS];
  184. atomic_t non_aql_packets;
  185. unsigned long flags;
  186. struct ewma_signal rssi;
  187. int inactive_count;
  188. u16 idx;
  189. u8 hw_key_idx;
  190. u8 hw_key_idx2;
  191. u8 sta:1;
  192. u8 ext_phy:1;
  193. u8 amsdu:1;
  194. u8 rx_check_pn;
  195. u8 rx_key_pn[IEEE80211_NUM_TIDS][6];
  196. u16 cipher;
  197. u32 tx_info;
  198. bool sw_iv;
  199. u8 packet_id;
  200. };
  201. struct mt76_txq {
  202. struct mt76_wcid *wcid;
  203. u16 agg_ssn;
  204. bool send_bar;
  205. bool aggr;
  206. };
  207. struct mt76_txwi_cache {
  208. struct list_head list;
  209. dma_addr_t dma_addr;
  210. struct sk_buff *skb;
  211. };
  212. struct mt76_rx_tid {
  213. struct rcu_head rcu_head;
  214. struct mt76_dev *dev;
  215. spinlock_t lock;
  216. struct delayed_work reorder_work;
  217. u16 head;
  218. u16 size;
  219. u16 nframes;
  220. u8 num;
  221. u8 started:1, stopped:1, timer_pending:1;
  222. struct sk_buff *reorder_buf[];
  223. };
  224. #define MT_TX_CB_DMA_DONE BIT(0)
  225. #define MT_TX_CB_TXS_DONE BIT(1)
  226. #define MT_TX_CB_TXS_FAILED BIT(2)
  227. #define MT_PACKET_ID_MASK GENMASK(6, 0)
  228. #define MT_PACKET_ID_NO_ACK 0
  229. #define MT_PACKET_ID_NO_SKB 1
  230. #define MT_PACKET_ID_FIRST 2
  231. #define MT_PACKET_ID_HAS_RATE BIT(7)
  232. #define MT_TX_STATUS_SKB_TIMEOUT HZ
  233. struct mt76_tx_cb {
  234. unsigned long jiffies;
  235. u16 wcid;
  236. u8 pktid;
  237. u8 flags;
  238. };
  239. enum {
  240. MT76_STATE_INITIALIZED,
  241. MT76_STATE_RUNNING,
  242. MT76_STATE_MCU_RUNNING,
  243. MT76_SCANNING,
  244. MT76_HW_SCANNING,
  245. MT76_HW_SCHED_SCANNING,
  246. MT76_RESTART,
  247. MT76_RESET,
  248. MT76_MCU_RESET,
  249. MT76_REMOVED,
  250. MT76_READING_STATS,
  251. MT76_STATE_POWER_OFF,
  252. MT76_STATE_SUSPEND,
  253. MT76_STATE_ROC,
  254. MT76_STATE_PM,
  255. };
  256. struct mt76_hw_cap {
  257. bool has_2ghz;
  258. bool has_5ghz;
  259. bool has_6ghz;
  260. };
  261. #define MT_DRV_TXWI_NO_FREE BIT(0)
  262. #define MT_DRV_TX_ALIGNED4_SKBS BIT(1)
  263. #define MT_DRV_SW_RX_AIRTIME BIT(2)
  264. #define MT_DRV_RX_DMA_HDR BIT(3)
  265. #define MT_DRV_HW_MGMT_TXQ BIT(4)
  266. #define MT_DRV_AMSDU_OFFLOAD BIT(5)
  267. struct mt76_driver_ops {
  268. u32 drv_flags;
  269. u32 survey_flags;
  270. u16 txwi_size;
  271. u16 token_size;
  272. u8 mcs_rates;
  273. void (*update_survey)(struct mt76_dev *dev);
  274. int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr,
  275. enum mt76_txq_id qid, struct mt76_wcid *wcid,
  276. struct ieee80211_sta *sta,
  277. struct mt76_tx_info *tx_info);
  278. void (*tx_complete_skb)(struct mt76_dev *dev,
  279. struct mt76_queue_entry *e);
  280. bool (*tx_status_data)(struct mt76_dev *dev, u8 *update);
  281. void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q,
  282. struct sk_buff *skb);
  283. void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q);
  284. void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta,
  285. bool ps);
  286. int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif,
  287. struct ieee80211_sta *sta);
  288. void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif,
  289. struct ieee80211_sta *sta);
  290. void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif,
  291. struct ieee80211_sta *sta);
  292. };
  293. struct mt76_channel_state {
  294. u64 cc_active;
  295. u64 cc_busy;
  296. u64 cc_rx;
  297. u64 cc_bss_rx;
  298. u64 cc_tx;
  299. s8 noise;
  300. };
  301. struct mt76_sband {
  302. struct ieee80211_supported_band sband;
  303. struct mt76_channel_state *chan;
  304. };
  305. struct mt76_rate_power {
  306. union {
  307. struct {
  308. s8 cck[4];
  309. s8 ofdm[8];
  310. s8 stbc[10];
  311. s8 ht[16];
  312. s8 vht[10];
  313. };
  314. s8 all[48];
  315. };
  316. };
  317. /* addr req mask */
  318. #define MT_VEND_TYPE_EEPROM BIT(31)
  319. #define MT_VEND_TYPE_CFG BIT(30)
  320. #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG)
  321. #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n))
  322. enum mt_vendor_req {
  323. MT_VEND_DEV_MODE = 0x1,
  324. MT_VEND_WRITE = 0x2,
  325. MT_VEND_POWER_ON = 0x4,
  326. MT_VEND_MULTI_WRITE = 0x6,
  327. MT_VEND_MULTI_READ = 0x7,
  328. MT_VEND_READ_EEPROM = 0x9,
  329. MT_VEND_WRITE_FCE = 0x42,
  330. MT_VEND_WRITE_CFG = 0x46,
  331. MT_VEND_READ_CFG = 0x47,
  332. MT_VEND_READ_EXT = 0x63,
  333. MT_VEND_WRITE_EXT = 0x66,
  334. MT_VEND_FEATURE_SET = 0x91,
  335. };
  336. enum mt76u_in_ep {
  337. MT_EP_IN_PKT_RX,
  338. MT_EP_IN_CMD_RESP,
  339. __MT_EP_IN_MAX,
  340. };
  341. enum mt76u_out_ep {
  342. MT_EP_OUT_INBAND_CMD,
  343. MT_EP_OUT_AC_BE,
  344. MT_EP_OUT_AC_BK,
  345. MT_EP_OUT_AC_VI,
  346. MT_EP_OUT_AC_VO,
  347. MT_EP_OUT_HCCA,
  348. __MT_EP_OUT_MAX,
  349. };
  350. struct mt76_mcu {
  351. struct mutex mutex;
  352. u32 msg_seq;
  353. int timeout;
  354. struct sk_buff_head res_q;
  355. wait_queue_head_t wait;
  356. };
  357. #define MT_TX_SG_MAX_SIZE 8
  358. #define MT_RX_SG_MAX_SIZE 4
  359. #define MT_NUM_TX_ENTRIES 256
  360. #define MT_NUM_RX_ENTRIES 128
  361. #define MCU_RESP_URB_SIZE 1024
  362. struct mt76_usb {
  363. struct mutex usb_ctrl_mtx;
  364. u8 *data;
  365. u16 data_len;
  366. struct mt76_worker status_worker;
  367. struct mt76_worker rx_worker;
  368. struct work_struct stat_work;
  369. u8 out_ep[__MT_EP_OUT_MAX];
  370. u8 in_ep[__MT_EP_IN_MAX];
  371. bool sg_en;
  372. struct mt76u_mcu {
  373. u8 *data;
  374. /* multiple reads */
  375. struct mt76_reg_pair *rp;
  376. int rp_len;
  377. u32 base;
  378. bool burst;
  379. } mcu;
  380. };
  381. #define MT76S_XMIT_BUF_SZ (16 * PAGE_SIZE)
  382. struct mt76_sdio {
  383. struct mt76_worker txrx_worker;
  384. struct mt76_worker status_worker;
  385. struct mt76_worker net_worker;
  386. struct work_struct stat_work;
  387. u8 *xmit_buf[IEEE80211_NUM_ACS + 2];
  388. struct sdio_func *func;
  389. void *intr_data;
  390. struct {
  391. int pse_data_quota;
  392. int ple_data_quota;
  393. int pse_mcu_quota;
  394. int deficit;
  395. } sched;
  396. };
  397. struct mt76_mmio {
  398. void __iomem *regs;
  399. spinlock_t irq_lock;
  400. u32 irqmask;
  401. };
  402. struct mt76_rx_status {
  403. union {
  404. struct mt76_wcid *wcid;
  405. u16 wcid_idx;
  406. };
  407. u32 reorder_time;
  408. u32 ampdu_ref;
  409. u32 timestamp;
  410. u8 iv[6];
  411. u8 ext_phy:1;
  412. u8 aggr:1;
  413. u8 qos_ctl;
  414. u16 seqno;
  415. u16 freq;
  416. u32 flag;
  417. u8 enc_flags;
  418. u8 encoding:2, bw:3, he_ru:3;
  419. u8 he_gi:2, he_dcm:1;
  420. u8 amsdu:1, first_amsdu:1, last_amsdu:1;
  421. u8 rate_idx;
  422. u8 nss;
  423. u8 band;
  424. s8 signal;
  425. u8 chains;
  426. s8 chain_signal[IEEE80211_MAX_CHAINS];
  427. };
  428. struct mt76_testmode_ops {
  429. int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state);
  430. int (*set_params)(struct mt76_phy *phy, struct nlattr **tb,
  431. enum mt76_testmode_state new_state);
  432. int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg);
  433. };
  434. struct mt76_testmode_data {
  435. enum mt76_testmode_state state;
  436. u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)];
  437. struct sk_buff *tx_skb;
  438. u32 tx_count;
  439. u16 tx_mpdu_len;
  440. u8 tx_rate_mode;
  441. u8 tx_rate_idx;
  442. u8 tx_rate_nss;
  443. u8 tx_rate_sgi;
  444. u8 tx_rate_ldpc;
  445. u8 tx_rate_stbc;
  446. u8 tx_ltf;
  447. u8 tx_antenna_mask;
  448. u8 tx_spe_idx;
  449. u8 tx_duty_cycle;
  450. u32 tx_time;
  451. u32 tx_ipg;
  452. u32 freq_offset;
  453. u8 tx_power[4];
  454. u8 tx_power_control;
  455. u32 tx_pending;
  456. u32 tx_queued;
  457. u16 tx_queued_limit;
  458. u32 tx_done;
  459. struct {
  460. u64 packets[__MT_RXQ_MAX];
  461. u64 fcs_error[__MT_RXQ_MAX];
  462. } rx_stats;
  463. };
  464. struct mt76_vif {
  465. u8 idx;
  466. u8 omac_idx;
  467. u8 band_idx;
  468. u8 wmm_idx;
  469. u8 scan_seq_num;
  470. };
  471. struct mt76_phy {
  472. struct ieee80211_hw *hw;
  473. struct mt76_dev *dev;
  474. void *priv;
  475. unsigned long state;
  476. struct mt76_queue *q_tx[__MT_TXQ_MAX];
  477. struct cfg80211_chan_def chandef;
  478. struct ieee80211_channel *main_chan;
  479. struct mt76_channel_state *chan_state;
  480. ktime_t survey_time;
  481. struct mt76_hw_cap cap;
  482. struct mt76_sband sband_2g;
  483. struct mt76_sband sband_5g;
  484. u8 macaddr[ETH_ALEN];
  485. int txpower_cur;
  486. u8 antenna_mask;
  487. u16 chainmask;
  488. #ifdef CONFIG_NL80211_TESTMODE
  489. struct mt76_testmode_data test;
  490. #endif
  491. struct delayed_work mac_work;
  492. u8 mac_work_count;
  493. struct {
  494. struct sk_buff *head;
  495. struct sk_buff **tail;
  496. u16 seqno;
  497. } rx_amsdu[__MT_RXQ_MAX];
  498. };
  499. struct mt76_dev {
  500. struct mt76_phy phy; /* must be first */
  501. struct mt76_phy *phy2;
  502. struct ieee80211_hw *hw;
  503. spinlock_t lock;
  504. spinlock_t cc_lock;
  505. u32 cur_cc_bss_rx;
  506. struct mt76_rx_status rx_ampdu_status;
  507. u32 rx_ampdu_len;
  508. u32 rx_ampdu_ref;
  509. struct mutex mutex;
  510. const struct mt76_bus_ops *bus;
  511. const struct mt76_driver_ops *drv;
  512. const struct mt76_mcu_ops *mcu_ops;
  513. struct device *dev;
  514. struct mt76_mcu mcu;
  515. struct net_device napi_dev;
  516. struct net_device tx_napi_dev;
  517. spinlock_t rx_lock;
  518. struct napi_struct napi[__MT_RXQ_MAX];
  519. struct sk_buff_head rx_skb[__MT_RXQ_MAX];
  520. struct list_head txwi_cache;
  521. struct mt76_queue *q_mcu[__MT_MCUQ_MAX];
  522. struct mt76_queue q_rx[__MT_RXQ_MAX];
  523. const struct mt76_queue_ops *queue_ops;
  524. int tx_dma_idx[4];
  525. struct mt76_worker tx_worker;
  526. struct napi_struct tx_napi;
  527. spinlock_t token_lock;
  528. struct idr token;
  529. int token_count;
  530. wait_queue_head_t tx_wait;
  531. struct sk_buff_head status_list;
  532. u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)];
  533. u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)];
  534. u32 vif_mask;
  535. struct mt76_wcid global_wcid;
  536. struct mt76_wcid __rcu *wcid[MT76_N_WCIDS];
  537. u32 rev;
  538. u32 aggr_stats[32];
  539. struct tasklet_struct pre_tbtt_tasklet;
  540. int beacon_int;
  541. u8 beacon_mask;
  542. struct debugfs_blob_wrapper eeprom;
  543. struct debugfs_blob_wrapper otp;
  544. struct mt76_rate_power rate_power;
  545. char alpha2[3];
  546. enum nl80211_dfs_regions region;
  547. u32 debugfs_reg;
  548. struct led_classdev led_cdev;
  549. char led_name[32];
  550. bool led_al;
  551. u8 led_pin;
  552. u8 csa_complete;
  553. u32 rxfilter;
  554. #ifdef CONFIG_NL80211_TESTMODE
  555. const struct mt76_testmode_ops *test_ops;
  556. struct {
  557. const char *name;
  558. u32 offset;
  559. } test_mtd;
  560. #endif
  561. struct workqueue_struct *wq;
  562. union {
  563. struct mt76_mmio mmio;
  564. struct mt76_usb usb;
  565. struct mt76_sdio sdio;
  566. };
  567. };
  568. struct mt76_power_limits {
  569. s8 cck[4];
  570. s8 ofdm[8];
  571. s8 mcs[4][10];
  572. s8 ru[7][12];
  573. };
  574. enum mt76_phy_type {
  575. MT_PHY_TYPE_CCK,
  576. MT_PHY_TYPE_OFDM,
  577. MT_PHY_TYPE_HT,
  578. MT_PHY_TYPE_HT_GF,
  579. MT_PHY_TYPE_VHT,
  580. MT_PHY_TYPE_HE_SU = 8,
  581. MT_PHY_TYPE_HE_EXT_SU,
  582. MT_PHY_TYPE_HE_TB,
  583. MT_PHY_TYPE_HE_MU,
  584. };
  585. #define CCK_RATE(_idx, _rate) { \
  586. .bitrate = _rate, \
  587. .flags = IEEE80211_RATE_SHORT_PREAMBLE, \
  588. .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \
  589. .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \
  590. }
  591. #define OFDM_RATE(_idx, _rate) { \
  592. .bitrate = _rate, \
  593. .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \
  594. .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \
  595. }
  596. extern struct ieee80211_rate mt76_rates[12];
  597. #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__)
  598. #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__)
  599. #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__)
  600. #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__)
  601. #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__)
  602. #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val)
  603. #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0)
  604. #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__)
  605. #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__)
  606. #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__)
  607. #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__)
  608. #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__)
  609. #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__)
  610. #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__)
  611. #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76))
  612. #define __mt76_mcu_restart(dev, ...) (dev)->mcu_ops->mcu_restart((dev))
  613. #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val)
  614. #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0)
  615. #define mt76_get_field(_dev, _reg, _field) \
  616. FIELD_GET(_field, mt76_rr(dev, _reg))
  617. #define mt76_rmw_field(_dev, _reg, _field, _val) \
  618. mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
  619. #define __mt76_rmw_field(_dev, _reg, _field, _val) \
  620. __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
  621. #define mt76_hw(dev) (dev)->mphy.hw
  622. static inline struct ieee80211_hw *
  623. mt76_wcid_hw(struct mt76_dev *dev, u16 wcid)
  624. {
  625. if (wcid <= MT76_N_WCIDS &&
  626. mt76_wcid_mask_test(dev->wcid_phy_mask, wcid))
  627. return dev->phy2->hw;
  628. return dev->phy.hw;
  629. }
  630. bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
  631. int timeout);
  632. #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__)
  633. bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
  634. int timeout);
  635. #define mt76_poll_msec(dev, ...) __mt76_poll_msec(&((dev)->mt76), __VA_ARGS__)
  636. void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs);
  637. void mt76_pci_disable_aspm(struct pci_dev *pdev);
  638. static inline u16 mt76_chip(struct mt76_dev *dev)
  639. {
  640. return dev->rev >> 16;
  641. }
  642. static inline u16 mt76_rev(struct mt76_dev *dev)
  643. {
  644. return dev->rev & 0xffff;
  645. }
  646. #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76))
  647. #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76))
  648. #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__)
  649. #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__)
  650. #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__)
  651. #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__)
  652. #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__)
  653. #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__)
  654. #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__)
  655. #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__)
  656. #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__)
  657. #define mt76_for_each_q_rx(dev, i) \
  658. for (i = 0; i < ARRAY_SIZE((dev)->q_rx) && \
  659. (dev)->q_rx[i].ndesc; i++)
  660. struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size,
  661. const struct ieee80211_ops *ops,
  662. const struct mt76_driver_ops *drv_ops);
  663. int mt76_register_device(struct mt76_dev *dev, bool vht,
  664. struct ieee80211_rate *rates, int n_rates);
  665. void mt76_unregister_device(struct mt76_dev *dev);
  666. void mt76_free_device(struct mt76_dev *dev);
  667. void mt76_unregister_phy(struct mt76_phy *phy);
  668. struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size,
  669. const struct ieee80211_ops *ops);
  670. int mt76_register_phy(struct mt76_phy *phy, bool vht,
  671. struct ieee80211_rate *rates, int n_rates);
  672. struct dentry *mt76_register_debugfs(struct mt76_dev *dev);
  673. int mt76_queues_read(struct seq_file *s, void *data);
  674. void mt76_seq_puts_array(struct seq_file *file, const char *str,
  675. s8 *val, int len);
  676. int mt76_eeprom_init(struct mt76_dev *dev, int len);
  677. void mt76_eeprom_override(struct mt76_phy *phy);
  678. int mt76_get_of_eeprom(struct mt76_dev *dev, void *data, int offset, int len);
  679. struct mt76_queue *
  680. mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc,
  681. int ring_base);
  682. static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx,
  683. int n_desc, int ring_base)
  684. {
  685. struct mt76_queue *q;
  686. q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base);
  687. if (IS_ERR(q))
  688. return PTR_ERR(q);
  689. q->qid = qid;
  690. phy->q_tx[qid] = q;
  691. return 0;
  692. }
  693. static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx,
  694. int n_desc, int ring_base)
  695. {
  696. struct mt76_queue *q;
  697. q = mt76_init_queue(dev, qid, idx, n_desc, ring_base);
  698. if (IS_ERR(q))
  699. return PTR_ERR(q);
  700. q->qid = __MT_TXQ_MAX + qid;
  701. dev->q_mcu[qid] = q;
  702. return 0;
  703. }
  704. static inline struct mt76_phy *
  705. mt76_dev_phy(struct mt76_dev *dev, bool phy_ext)
  706. {
  707. if (phy_ext && dev->phy2)
  708. return dev->phy2;
  709. return &dev->phy;
  710. }
  711. static inline struct ieee80211_hw *
  712. mt76_phy_hw(struct mt76_dev *dev, bool phy_ext)
  713. {
  714. return mt76_dev_phy(dev, phy_ext)->hw;
  715. }
  716. static inline u8 *
  717. mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t)
  718. {
  719. return (u8 *)t - dev->drv->txwi_size;
  720. }
  721. /* increment with wrap-around */
  722. static inline int mt76_incr(int val, int size)
  723. {
  724. return (val + 1) & (size - 1);
  725. }
  726. /* decrement with wrap-around */
  727. static inline int mt76_decr(int val, int size)
  728. {
  729. return (val - 1) & (size - 1);
  730. }
  731. u8 mt76_ac_to_hwq(u8 ac);
  732. static inline struct ieee80211_txq *
  733. mtxq_to_txq(struct mt76_txq *mtxq)
  734. {
  735. void *ptr = mtxq;
  736. return container_of(ptr, struct ieee80211_txq, drv_priv);
  737. }
  738. static inline struct ieee80211_sta *
  739. wcid_to_sta(struct mt76_wcid *wcid)
  740. {
  741. void *ptr = wcid;
  742. if (!wcid || !wcid->sta)
  743. return NULL;
  744. return container_of(ptr, struct ieee80211_sta, drv_priv);
  745. }
  746. static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb)
  747. {
  748. BUILD_BUG_ON(sizeof(struct mt76_tx_cb) >
  749. sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data));
  750. return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data);
  751. }
  752. static inline void *mt76_skb_get_hdr(struct sk_buff *skb)
  753. {
  754. struct mt76_rx_status mstat;
  755. u8 *data = skb->data;
  756. /* Alignment concerns */
  757. BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4);
  758. BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4);
  759. mstat = *((struct mt76_rx_status *)skb->cb);
  760. if (mstat.flag & RX_FLAG_RADIOTAP_HE)
  761. data += sizeof(struct ieee80211_radiotap_he);
  762. if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU)
  763. data += sizeof(struct ieee80211_radiotap_he_mu);
  764. return data;
  765. }
  766. static inline void mt76_insert_hdr_pad(struct sk_buff *skb)
  767. {
  768. int len = ieee80211_get_hdrlen_from_skb(skb);
  769. if (len % 4 == 0)
  770. return;
  771. skb_push(skb, 2);
  772. memmove(skb->data, skb->data + 2, len);
  773. skb->data[len] = 0;
  774. skb->data[len + 1] = 0;
  775. }
  776. static inline bool mt76_is_skb_pktid(u8 pktid)
  777. {
  778. if (pktid & MT_PACKET_ID_HAS_RATE)
  779. return false;
  780. return pktid >= MT_PACKET_ID_FIRST;
  781. }
  782. static inline u8 mt76_tx_power_nss_delta(u8 nss)
  783. {
  784. static const u8 nss_delta[4] = { 0, 6, 9, 12 };
  785. return nss_delta[nss - 1];
  786. }
  787. static inline bool mt76_testmode_enabled(struct mt76_phy *phy)
  788. {
  789. #ifdef CONFIG_NL80211_TESTMODE
  790. return phy->test.state != MT76_TM_STATE_OFF;
  791. #else
  792. return false;
  793. #endif
  794. }
  795. static inline bool mt76_is_testmode_skb(struct mt76_dev *dev,
  796. struct sk_buff *skb,
  797. struct ieee80211_hw **hw)
  798. {
  799. #ifdef CONFIG_NL80211_TESTMODE
  800. if (skb == dev->phy.test.tx_skb)
  801. *hw = dev->phy.hw;
  802. else if (dev->phy2 && skb == dev->phy2->test.tx_skb)
  803. *hw = dev->phy2->hw;
  804. else
  805. return false;
  806. return true;
  807. #else
  808. return false;
  809. #endif
  810. }
  811. void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb);
  812. void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta,
  813. struct mt76_wcid *wcid, struct sk_buff *skb);
  814. void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq);
  815. void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta,
  816. bool send_bar);
  817. void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb);
  818. void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid);
  819. void mt76_txq_schedule_all(struct mt76_phy *phy);
  820. void mt76_tx_worker_run(struct mt76_dev *dev);
  821. void mt76_tx_worker(struct mt76_worker *w);
  822. void mt76_release_buffered_frames(struct ieee80211_hw *hw,
  823. struct ieee80211_sta *sta,
  824. u16 tids, int nframes,
  825. enum ieee80211_frame_release_type reason,
  826. bool more_data);
  827. bool mt76_has_tx_pending(struct mt76_phy *phy);
  828. void mt76_set_channel(struct mt76_phy *phy);
  829. void mt76_update_survey(struct mt76_dev *dev);
  830. void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time);
  831. int mt76_get_survey(struct ieee80211_hw *hw, int idx,
  832. struct survey_info *survey);
  833. void mt76_set_stream_caps(struct mt76_phy *phy, bool vht);
  834. int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid,
  835. u16 ssn, u16 size);
  836. void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid);
  837. void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid,
  838. struct ieee80211_key_conf *key);
  839. void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list)
  840. __acquires(&dev->status_list.lock);
  841. void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list)
  842. __releases(&dev->status_list.lock);
  843. int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid,
  844. struct sk_buff *skb);
  845. struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev,
  846. struct mt76_wcid *wcid, int pktid,
  847. struct sk_buff_head *list);
  848. void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb,
  849. struct sk_buff_head *list);
  850. void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb,
  851. struct list_head *free_list);
  852. static inline void
  853. mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb)
  854. {
  855. __mt76_tx_complete_skb(dev, wcid, skb, NULL);
  856. }
  857. void mt76_tx_status_check(struct mt76_dev *dev, struct mt76_wcid *wcid,
  858. bool flush);
  859. int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  860. struct ieee80211_sta *sta,
  861. enum ieee80211_sta_state old_state,
  862. enum ieee80211_sta_state new_state);
  863. void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif,
  864. struct ieee80211_sta *sta);
  865. void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  866. struct ieee80211_sta *sta);
  867. int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy);
  868. int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  869. int *dbm);
  870. void mt76_csa_check(struct mt76_dev *dev);
  871. void mt76_csa_finish(struct mt76_dev *dev);
  872. int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant);
  873. int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set);
  874. void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id);
  875. int mt76_get_rate(struct mt76_dev *dev,
  876. struct ieee80211_supported_band *sband,
  877. int idx, bool cck);
  878. void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  879. const u8 *mac);
  880. void mt76_sw_scan_complete(struct ieee80211_hw *hw,
  881. struct ieee80211_vif *vif);
  882. int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  883. void *data, int len);
  884. int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb,
  885. struct netlink_callback *cb, void *data, int len);
  886. int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state);
  887. int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len);
  888. static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable)
  889. {
  890. #ifdef CONFIG_NL80211_TESTMODE
  891. enum mt76_testmode_state state = MT76_TM_STATE_IDLE;
  892. if (disable || phy->test.state == MT76_TM_STATE_OFF)
  893. state = MT76_TM_STATE_OFF;
  894. mt76_testmode_set_state(phy, state);
  895. #endif
  896. }
  897. /* internal */
  898. static inline struct ieee80211_hw *
  899. mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb)
  900. {
  901. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  902. struct ieee80211_hw *hw = dev->phy.hw;
  903. if ((info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY) && dev->phy2)
  904. hw = dev->phy2->hw;
  905. info->hw_queue &= ~MT_TX_HW_QUEUE_EXT_PHY;
  906. return hw;
  907. }
  908. void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
  909. void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames,
  910. struct napi_struct *napi);
  911. void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
  912. struct napi_struct *napi);
  913. void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames);
  914. void mt76_testmode_tx_pending(struct mt76_phy *phy);
  915. void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q,
  916. struct mt76_queue_entry *e);
  917. /* usb */
  918. static inline bool mt76u_urb_error(struct urb *urb)
  919. {
  920. return urb->status &&
  921. urb->status != -ECONNRESET &&
  922. urb->status != -ESHUTDOWN &&
  923. urb->status != -ENOENT;
  924. }
  925. /* Map hardware queues to usb endpoints */
  926. static inline u8 q2ep(u8 qid)
  927. {
  928. /* TODO: take management packets to queue 5 */
  929. return qid + 1;
  930. }
  931. static inline int
  932. mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len,
  933. int timeout, int ep)
  934. {
  935. struct usb_interface *uintf = to_usb_interface(dev->dev);
  936. struct usb_device *udev = interface_to_usbdev(uintf);
  937. struct mt76_usb *usb = &dev->usb;
  938. unsigned int pipe;
  939. if (actual_len)
  940. pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]);
  941. else
  942. pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]);
  943. return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout);
  944. }
  945. int mt76_skb_adjust_pad(struct sk_buff *skb, int pad);
  946. int mt76u_vendor_request(struct mt76_dev *dev, u8 req,
  947. u8 req_type, u16 val, u16 offset,
  948. void *buf, size_t len);
  949. void mt76u_single_wr(struct mt76_dev *dev, const u8 req,
  950. const u16 offset, const u32 val);
  951. int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf,
  952. bool ext);
  953. int mt76u_alloc_mcu_queue(struct mt76_dev *dev);
  954. int mt76u_alloc_queues(struct mt76_dev *dev);
  955. void mt76u_stop_tx(struct mt76_dev *dev);
  956. void mt76u_stop_rx(struct mt76_dev *dev);
  957. int mt76u_resume_rx(struct mt76_dev *dev);
  958. void mt76u_queues_deinit(struct mt76_dev *dev);
  959. int mt76s_init(struct mt76_dev *dev, struct sdio_func *func,
  960. const struct mt76_bus_ops *bus_ops);
  961. int mt76s_alloc_queues(struct mt76_dev *dev);
  962. void mt76s_deinit(struct mt76_dev *dev);
  963. struct sk_buff *
  964. mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data,
  965. int data_len);
  966. void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb);
  967. struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev,
  968. unsigned long expires);
  969. int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data,
  970. int len, bool wait_resp, struct sk_buff **ret);
  971. int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb,
  972. int cmd, bool wait_resp, struct sk_buff **ret);
  973. int mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data,
  974. int len);
  975. static inline int
  976. mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len,
  977. bool wait_resp)
  978. {
  979. return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL);
  980. }
  981. static inline int
  982. mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd,
  983. bool wait_resp)
  984. {
  985. return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL);
  986. }
  987. void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set);
  988. s8 mt76_get_rate_power_limits(struct mt76_phy *phy,
  989. struct ieee80211_channel *chan,
  990. struct mt76_power_limits *dest,
  991. s8 target_power);
  992. struct mt76_txwi_cache *
  993. mt76_token_release(struct mt76_dev *dev, int token, bool *wake);
  994. int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi);
  995. void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked);
  996. static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked)
  997. {
  998. spin_lock_bh(&dev->token_lock);
  999. __mt76_set_tx_blocked(dev, blocked);
  1000. spin_unlock_bh(&dev->token_lock);
  1001. }
  1002. static inline int
  1003. mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi)
  1004. {
  1005. int token;
  1006. spin_lock_bh(&dev->token_lock);
  1007. token = idr_alloc(&dev->token, *ptxwi, 0, dev->drv->token_size,
  1008. GFP_ATOMIC);
  1009. spin_unlock_bh(&dev->token_lock);
  1010. return token;
  1011. }
  1012. static inline struct mt76_txwi_cache *
  1013. mt76_token_put(struct mt76_dev *dev, int token)
  1014. {
  1015. struct mt76_txwi_cache *txwi;
  1016. spin_lock_bh(&dev->token_lock);
  1017. txwi = idr_remove(&dev->token, token);
  1018. spin_unlock_bh(&dev->token_lock);
  1019. return txwi;
  1020. }
  1021. static inline int
  1022. mt76_get_next_pkt_id(struct mt76_wcid *wcid)
  1023. {
  1024. wcid->packet_id = (wcid->packet_id + 1) & MT_PACKET_ID_MASK;
  1025. if (wcid->packet_id == MT_PACKET_ID_NO_ACK ||
  1026. wcid->packet_id == MT_PACKET_ID_NO_SKB)
  1027. wcid->packet_id = MT_PACKET_ID_FIRST;
  1028. return wcid->packet_id;
  1029. }
  1030. #endif