mt76_connac_mcu.h 23 KB

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  1. /* SPDX-License-Identifier: ISC */
  2. /* Copyright (C) 2020 MediaTek Inc. */
  3. #ifndef __MT76_CONNAC_MCU_H
  4. #define __MT76_CONNAC_MCU_H
  5. #include "mt76_connac.h"
  6. struct tlv {
  7. __le16 tag;
  8. __le16 len;
  9. } __packed;
  10. /* sta_rec */
  11. struct sta_ntlv_hdr {
  12. u8 rsv[2];
  13. __le16 tlv_num;
  14. } __packed;
  15. struct sta_req_hdr {
  16. u8 bss_idx;
  17. u8 wlan_idx_lo;
  18. __le16 tlv_num;
  19. u8 is_tlv_append;
  20. u8 muar_idx;
  21. u8 wlan_idx_hi;
  22. u8 rsv;
  23. } __packed;
  24. struct sta_rec_basic {
  25. __le16 tag;
  26. __le16 len;
  27. __le32 conn_type;
  28. u8 conn_state;
  29. u8 qos;
  30. __le16 aid;
  31. u8 peer_addr[ETH_ALEN];
  32. #define EXTRA_INFO_VER BIT(0)
  33. #define EXTRA_INFO_NEW BIT(1)
  34. __le16 extra_info;
  35. } __packed;
  36. struct sta_rec_ht {
  37. __le16 tag;
  38. __le16 len;
  39. __le16 ht_cap;
  40. u16 rsv;
  41. } __packed;
  42. struct sta_rec_vht {
  43. __le16 tag;
  44. __le16 len;
  45. __le32 vht_cap;
  46. __le16 vht_rx_mcs_map;
  47. __le16 vht_tx_mcs_map;
  48. /* mt7921 */
  49. u8 rts_bw_sig;
  50. u8 rsv[3];
  51. } __packed;
  52. struct sta_rec_uapsd {
  53. __le16 tag;
  54. __le16 len;
  55. u8 dac_map;
  56. u8 tac_map;
  57. u8 max_sp;
  58. u8 rsv0;
  59. __le16 listen_interval;
  60. u8 rsv1[2];
  61. } __packed;
  62. struct sta_rec_ba {
  63. __le16 tag;
  64. __le16 len;
  65. u8 tid;
  66. u8 ba_type;
  67. u8 amsdu;
  68. u8 ba_en;
  69. __le16 ssn;
  70. __le16 winsize;
  71. } __packed;
  72. struct sta_rec_he {
  73. __le16 tag;
  74. __le16 len;
  75. __le32 he_cap;
  76. u8 t_frame_dur;
  77. u8 max_ampdu_exp;
  78. u8 bw_set;
  79. u8 device_class;
  80. u8 dcm_tx_mode;
  81. u8 dcm_tx_max_nss;
  82. u8 dcm_rx_mode;
  83. u8 dcm_rx_max_nss;
  84. u8 dcm_max_ru;
  85. u8 punc_pream_rx;
  86. u8 pkt_ext;
  87. u8 rsv1;
  88. __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
  89. u8 rsv2[2];
  90. } __packed;
  91. struct sta_rec_amsdu {
  92. __le16 tag;
  93. __le16 len;
  94. u8 max_amsdu_num;
  95. u8 max_mpdu_size;
  96. u8 amsdu_en;
  97. u8 rsv;
  98. } __packed;
  99. struct sta_rec_state {
  100. __le16 tag;
  101. __le16 len;
  102. __le32 flags;
  103. u8 state;
  104. u8 vht_opmode;
  105. u8 action;
  106. u8 rsv[1];
  107. } __packed;
  108. #define HT_MCS_MASK_NUM 10
  109. struct sta_rec_ra_info {
  110. __le16 tag;
  111. __le16 len;
  112. __le16 legacy;
  113. u8 rx_mcs_bitmask[HT_MCS_MASK_NUM];
  114. } __packed;
  115. struct sta_rec_phy {
  116. __le16 tag;
  117. __le16 len;
  118. __le16 basic_rate;
  119. u8 phy_type;
  120. u8 ampdu;
  121. u8 rts_policy;
  122. u8 rcpi;
  123. u8 rsv[2];
  124. } __packed;
  125. /* wtbl_rec */
  126. struct wtbl_req_hdr {
  127. u8 wlan_idx_lo;
  128. u8 operation;
  129. __le16 tlv_num;
  130. u8 wlan_idx_hi;
  131. u8 rsv[3];
  132. } __packed;
  133. struct wtbl_generic {
  134. __le16 tag;
  135. __le16 len;
  136. u8 peer_addr[ETH_ALEN];
  137. u8 muar_idx;
  138. u8 skip_tx;
  139. u8 cf_ack;
  140. u8 qos;
  141. u8 mesh;
  142. u8 adm;
  143. __le16 partial_aid;
  144. u8 baf_en;
  145. u8 aad_om;
  146. } __packed;
  147. struct wtbl_rx {
  148. __le16 tag;
  149. __le16 len;
  150. u8 rcid;
  151. u8 rca1;
  152. u8 rca2;
  153. u8 rv;
  154. u8 rsv[4];
  155. } __packed;
  156. struct wtbl_ht {
  157. __le16 tag;
  158. __le16 len;
  159. u8 ht;
  160. u8 ldpc;
  161. u8 af;
  162. u8 mm;
  163. u8 rsv[4];
  164. } __packed;
  165. struct wtbl_vht {
  166. __le16 tag;
  167. __le16 len;
  168. u8 ldpc;
  169. u8 dyn_bw;
  170. u8 vht;
  171. u8 txop_ps;
  172. u8 rsv[4];
  173. } __packed;
  174. struct wtbl_tx_ps {
  175. __le16 tag;
  176. __le16 len;
  177. u8 txps;
  178. u8 rsv[3];
  179. } __packed;
  180. struct wtbl_hdr_trans {
  181. __le16 tag;
  182. __le16 len;
  183. u8 to_ds;
  184. u8 from_ds;
  185. u8 disable_rx_trans;
  186. u8 rsv;
  187. } __packed;
  188. struct wtbl_ba {
  189. __le16 tag;
  190. __le16 len;
  191. /* common */
  192. u8 tid;
  193. u8 ba_type;
  194. u8 rsv0[2];
  195. /* originator only */
  196. __le16 sn;
  197. u8 ba_en;
  198. u8 ba_winsize_idx;
  199. __le16 ba_winsize;
  200. /* recipient only */
  201. u8 peer_addr[ETH_ALEN];
  202. u8 rst_ba_tid;
  203. u8 rst_ba_sel;
  204. u8 rst_ba_sb;
  205. u8 band_idx;
  206. u8 rsv1[4];
  207. } __packed;
  208. struct wtbl_smps {
  209. __le16 tag;
  210. __le16 len;
  211. u8 smps;
  212. u8 rsv[3];
  213. } __packed;
  214. /* mt7615 only */
  215. struct wtbl_bf {
  216. __le16 tag;
  217. __le16 len;
  218. u8 ibf;
  219. u8 ebf;
  220. u8 ibf_vht;
  221. u8 ebf_vht;
  222. u8 gid;
  223. u8 pfmu_idx;
  224. u8 rsv[2];
  225. } __packed;
  226. struct wtbl_pn {
  227. __le16 tag;
  228. __le16 len;
  229. u8 pn[6];
  230. u8 rsv[2];
  231. } __packed;
  232. struct wtbl_spe {
  233. __le16 tag;
  234. __le16 len;
  235. u8 spe_idx;
  236. u8 rsv[3];
  237. } __packed;
  238. struct wtbl_raw {
  239. __le16 tag;
  240. __le16 len;
  241. u8 wtbl_idx;
  242. u8 dw;
  243. u8 rsv[2];
  244. __le32 msk;
  245. __le32 val;
  246. } __packed;
  247. #define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \
  248. sizeof(struct wtbl_generic) + \
  249. sizeof(struct wtbl_rx) + \
  250. sizeof(struct wtbl_ht) + \
  251. sizeof(struct wtbl_vht) + \
  252. sizeof(struct wtbl_tx_ps) + \
  253. sizeof(struct wtbl_hdr_trans) +\
  254. sizeof(struct wtbl_ba) + \
  255. sizeof(struct wtbl_bf) + \
  256. sizeof(struct wtbl_smps) + \
  257. sizeof(struct wtbl_pn) + \
  258. sizeof(struct wtbl_spe))
  259. #define MT76_CONNAC_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \
  260. sizeof(struct sta_rec_basic) + \
  261. sizeof(struct sta_rec_ht) + \
  262. sizeof(struct sta_rec_he) + \
  263. sizeof(struct sta_rec_ba) + \
  264. sizeof(struct sta_rec_vht) + \
  265. sizeof(struct sta_rec_uapsd) + \
  266. sizeof(struct sta_rec_amsdu) + \
  267. sizeof(struct tlv) + \
  268. MT76_CONNAC_WTBL_UPDATE_MAX_SIZE)
  269. enum {
  270. STA_REC_BASIC,
  271. STA_REC_RA,
  272. STA_REC_RA_CMM_INFO,
  273. STA_REC_RA_UPDATE,
  274. STA_REC_BF,
  275. STA_REC_AMSDU,
  276. STA_REC_BA,
  277. STA_REC_STATE,
  278. STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */
  279. STA_REC_HT,
  280. STA_REC_VHT,
  281. STA_REC_APPS,
  282. STA_REC_KEY,
  283. STA_REC_WTBL,
  284. STA_REC_HE,
  285. STA_REC_HW_AMSDU,
  286. STA_REC_WTBL_AADOM,
  287. STA_REC_KEY_V2,
  288. STA_REC_MURU,
  289. STA_REC_MUEDCA,
  290. STA_REC_BFEE,
  291. STA_REC_PHY = 0x15,
  292. STA_REC_MAX_NUM
  293. };
  294. enum {
  295. WTBL_GENERIC,
  296. WTBL_RX,
  297. WTBL_HT,
  298. WTBL_VHT,
  299. WTBL_PEER_PS, /* not used */
  300. WTBL_TX_PS,
  301. WTBL_HDR_TRANS,
  302. WTBL_SEC_KEY,
  303. WTBL_BA,
  304. WTBL_RDG, /* obsoleted */
  305. WTBL_PROTECT, /* not used */
  306. WTBL_CLEAR, /* not used */
  307. WTBL_BF,
  308. WTBL_SMPS,
  309. WTBL_RAW_DATA, /* debug only */
  310. WTBL_PN,
  311. WTBL_SPE,
  312. WTBL_MAX_NUM
  313. };
  314. #define STA_TYPE_STA BIT(0)
  315. #define STA_TYPE_AP BIT(1)
  316. #define STA_TYPE_ADHOC BIT(2)
  317. #define STA_TYPE_WDS BIT(4)
  318. #define STA_TYPE_BC BIT(5)
  319. #define NETWORK_INFRA BIT(16)
  320. #define NETWORK_P2P BIT(17)
  321. #define NETWORK_IBSS BIT(18)
  322. #define NETWORK_WDS BIT(21)
  323. #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA)
  324. #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA)
  325. #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P)
  326. #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P)
  327. #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS)
  328. #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS)
  329. #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA)
  330. #define CONN_STATE_DISCONNECT 0
  331. #define CONN_STATE_CONNECT 1
  332. #define CONN_STATE_PORT_SECURE 2
  333. /* HE MAC */
  334. #define STA_REC_HE_CAP_HTC BIT(0)
  335. #define STA_REC_HE_CAP_BQR BIT(1)
  336. #define STA_REC_HE_CAP_BSR BIT(2)
  337. #define STA_REC_HE_CAP_OM BIT(3)
  338. #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4)
  339. /* HE PHY */
  340. #define STA_REC_HE_CAP_DUAL_BAND BIT(5)
  341. #define STA_REC_HE_CAP_LDPC BIT(6)
  342. #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7)
  343. #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8)
  344. /* STBC */
  345. #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9)
  346. #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10)
  347. #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11)
  348. #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12)
  349. /* GI */
  350. #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13)
  351. #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14)
  352. #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15)
  353. #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16)
  354. #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17)
  355. /* 242 TONE */
  356. #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18)
  357. #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19)
  358. #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20)
  359. #define PHY_MODE_A BIT(0)
  360. #define PHY_MODE_B BIT(1)
  361. #define PHY_MODE_G BIT(2)
  362. #define PHY_MODE_GN BIT(3)
  363. #define PHY_MODE_AN BIT(4)
  364. #define PHY_MODE_AC BIT(5)
  365. #define PHY_MODE_AX_24G BIT(6)
  366. #define PHY_MODE_AX_5G BIT(7)
  367. #define PHY_MODE_AX_6G BIT(8)
  368. #define MODE_CCK BIT(0)
  369. #define MODE_OFDM BIT(1)
  370. #define MODE_HT BIT(2)
  371. #define MODE_VHT BIT(3)
  372. #define MODE_HE BIT(4)
  373. enum {
  374. PHY_TYPE_HR_DSSS_INDEX = 0,
  375. PHY_TYPE_ERP_INDEX,
  376. PHY_TYPE_ERP_P2P_INDEX,
  377. PHY_TYPE_OFDM_INDEX,
  378. PHY_TYPE_HT_INDEX,
  379. PHY_TYPE_VHT_INDEX,
  380. PHY_TYPE_HE_INDEX,
  381. PHY_TYPE_INDEX_NUM
  382. };
  383. #define PHY_TYPE_BIT_HR_DSSS BIT(PHY_TYPE_HR_DSSS_INDEX)
  384. #define PHY_TYPE_BIT_ERP BIT(PHY_TYPE_ERP_INDEX)
  385. #define PHY_TYPE_BIT_OFDM BIT(PHY_TYPE_OFDM_INDEX)
  386. #define PHY_TYPE_BIT_HT BIT(PHY_TYPE_HT_INDEX)
  387. #define PHY_TYPE_BIT_VHT BIT(PHY_TYPE_VHT_INDEX)
  388. #define PHY_TYPE_BIT_HE BIT(PHY_TYPE_HE_INDEX)
  389. #define MT_WTBL_RATE_TX_MODE GENMASK(9, 6)
  390. #define MT_WTBL_RATE_MCS GENMASK(5, 0)
  391. #define MT_WTBL_RATE_NSS GENMASK(12, 10)
  392. #define MT_WTBL_RATE_HE_GI GENMASK(7, 4)
  393. #define MT_WTBL_RATE_GI GENMASK(3, 0)
  394. #define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5)
  395. #define MT_WTBL_W5_SHORT_GI_20 BIT(8)
  396. #define MT_WTBL_W5_SHORT_GI_40 BIT(9)
  397. #define MT_WTBL_W5_SHORT_GI_80 BIT(10)
  398. #define MT_WTBL_W5_SHORT_GI_160 BIT(11)
  399. #define MT_WTBL_W5_BW_CAP GENMASK(13, 12)
  400. #define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23)
  401. #define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26)
  402. #define MT_WTBL_W5_RATE_IDX GENMASK(31, 29)
  403. enum {
  404. WTBL_RESET_AND_SET = 1,
  405. WTBL_SET,
  406. WTBL_QUERY,
  407. WTBL_RESET_ALL
  408. };
  409. enum {
  410. MT_BA_TYPE_INVALID,
  411. MT_BA_TYPE_ORIGINATOR,
  412. MT_BA_TYPE_RECIPIENT
  413. };
  414. enum {
  415. RST_BA_MAC_TID_MATCH,
  416. RST_BA_MAC_MATCH,
  417. RST_BA_NO_MATCH
  418. };
  419. enum {
  420. DEV_INFO_ACTIVE,
  421. DEV_INFO_MAX_NUM
  422. };
  423. #define MCU_CMD_ACK BIT(0)
  424. #define MCU_CMD_UNI BIT(1)
  425. #define MCU_CMD_QUERY BIT(2)
  426. #define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | \
  427. MCU_CMD_QUERY)
  428. #define MCU_FW_PREFIX BIT(31)
  429. #define MCU_UNI_PREFIX BIT(30)
  430. #define MCU_CE_PREFIX BIT(29)
  431. #define MCU_QUERY_PREFIX BIT(28)
  432. #define MCU_CMD_MASK ~(MCU_FW_PREFIX | MCU_UNI_PREFIX | \
  433. MCU_CE_PREFIX | MCU_QUERY_PREFIX)
  434. #define MCU_QUERY_MASK BIT(16)
  435. enum {
  436. MCU_EXT_CMD_EFUSE_ACCESS = 0x01,
  437. MCU_EXT_CMD_RF_REG_ACCESS = 0x02,
  438. MCU_EXT_CMD_PM_STATE_CTRL = 0x07,
  439. MCU_EXT_CMD_CHANNEL_SWITCH = 0x08,
  440. MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11,
  441. MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
  442. MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
  443. MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
  444. MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26,
  445. MCU_EXT_CMD_EDCA_UPDATE = 0x27,
  446. MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A,
  447. MCU_EXT_CMD_GET_TEMP = 0x2c,
  448. MCU_EXT_CMD_WTBL_UPDATE = 0x32,
  449. MCU_EXT_CMD_SET_RDD_CTRL = 0x3a,
  450. MCU_EXT_CMD_ATE_CTRL = 0x3d,
  451. MCU_EXT_CMD_PROTECT_CTRL = 0x3e,
  452. MCU_EXT_CMD_DBDC_CTRL = 0x45,
  453. MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
  454. MCU_EXT_CMD_RX_HDR_TRANS = 0x47,
  455. MCU_EXT_CMD_MUAR_UPDATE = 0x48,
  456. MCU_EXT_CMD_BCN_OFFLOAD = 0x49,
  457. MCU_EXT_CMD_SET_RX_PATH = 0x4e,
  458. MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
  459. MCU_EXT_CMD_RXDCOC_CAL = 0x59,
  460. MCU_EXT_CMD_TXDPD_CAL = 0x60,
  461. MCU_EXT_CMD_SET_RDD_TH = 0x7c,
  462. MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d,
  463. };
  464. enum {
  465. MCU_UNI_CMD_DEV_INFO_UPDATE = MCU_UNI_PREFIX | 0x01,
  466. MCU_UNI_CMD_BSS_INFO_UPDATE = MCU_UNI_PREFIX | 0x02,
  467. MCU_UNI_CMD_STA_REC_UPDATE = MCU_UNI_PREFIX | 0x03,
  468. MCU_UNI_CMD_SUSPEND = MCU_UNI_PREFIX | 0x05,
  469. MCU_UNI_CMD_OFFLOAD = MCU_UNI_PREFIX | 0x06,
  470. MCU_UNI_CMD_HIF_CTRL = MCU_UNI_PREFIX | 0x07,
  471. };
  472. enum {
  473. MCU_CMD_TARGET_ADDRESS_LEN_REQ = MCU_FW_PREFIX | 0x01,
  474. MCU_CMD_FW_START_REQ = MCU_FW_PREFIX | 0x02,
  475. MCU_CMD_INIT_ACCESS_REG = 0x3,
  476. MCU_CMD_NIC_POWER_CTRL = MCU_FW_PREFIX | 0x4,
  477. MCU_CMD_PATCH_START_REQ = MCU_FW_PREFIX | 0x05,
  478. MCU_CMD_PATCH_FINISH_REQ = MCU_FW_PREFIX | 0x07,
  479. MCU_CMD_PATCH_SEM_CONTROL = MCU_FW_PREFIX | 0x10,
  480. MCU_CMD_EXT_CID = 0xed,
  481. MCU_CMD_FW_SCATTER = MCU_FW_PREFIX | 0xee,
  482. MCU_CMD_RESTART_DL_REQ = MCU_FW_PREFIX | 0xef,
  483. };
  484. /* offload mcu commands */
  485. enum {
  486. MCU_CMD_START_HW_SCAN = MCU_CE_PREFIX | 0x03,
  487. MCU_CMD_SET_PS_PROFILE = MCU_CE_PREFIX | 0x05,
  488. MCU_CMD_SET_CHAN_DOMAIN = MCU_CE_PREFIX | 0x0f,
  489. MCU_CMD_SET_BSS_CONNECTED = MCU_CE_PREFIX | 0x16,
  490. MCU_CMD_SET_BSS_ABORT = MCU_CE_PREFIX | 0x17,
  491. MCU_CMD_CANCEL_HW_SCAN = MCU_CE_PREFIX | 0x1b,
  492. MCU_CMD_SET_ROC = MCU_CE_PREFIX | 0x1d,
  493. MCU_CMD_SET_P2P_OPPPS = MCU_CE_PREFIX | 0x33,
  494. MCU_CMD_SET_RATE_TX_POWER = MCU_CE_PREFIX | 0x5d,
  495. MCU_CMD_SCHED_SCAN_ENABLE = MCU_CE_PREFIX | 0x61,
  496. MCU_CMD_SCHED_SCAN_REQ = MCU_CE_PREFIX | 0x62,
  497. MCU_CMD_REG_WRITE = MCU_CE_PREFIX | 0xc0,
  498. MCU_CMD_REG_READ = MCU_CE_PREFIX | MCU_QUERY_MASK | 0xc0,
  499. MCU_CMD_CHIP_CONFIG = MCU_CE_PREFIX | 0xca,
  500. MCU_CMD_FWLOG_2_HOST = MCU_CE_PREFIX | 0xc5,
  501. MCU_CMD_GET_WTBL = MCU_CE_PREFIX | 0xcd,
  502. };
  503. enum {
  504. PATCH_SEM_RELEASE,
  505. PATCH_SEM_GET
  506. };
  507. enum {
  508. UNI_BSS_INFO_BASIC = 0,
  509. UNI_BSS_INFO_RLM = 2,
  510. UNI_BSS_INFO_HE_BASIC = 5,
  511. UNI_BSS_INFO_BCN_CONTENT = 7,
  512. UNI_BSS_INFO_QBSS = 15,
  513. UNI_BSS_INFO_UAPSD = 19,
  514. UNI_BSS_INFO_PS = 21,
  515. UNI_BSS_INFO_BCNFT = 22,
  516. };
  517. enum {
  518. UNI_OFFLOAD_OFFLOAD_ARP,
  519. UNI_OFFLOAD_OFFLOAD_ND,
  520. UNI_OFFLOAD_OFFLOAD_GTK_REKEY,
  521. UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT,
  522. };
  523. enum {
  524. UNI_SUSPEND_MODE_SETTING,
  525. UNI_SUSPEND_WOW_CTRL,
  526. UNI_SUSPEND_WOW_GPIO_PARAM,
  527. UNI_SUSPEND_WOW_WAKEUP_PORT,
  528. UNI_SUSPEND_WOW_PATTERN,
  529. };
  530. enum {
  531. WOW_USB = 1,
  532. WOW_PCIE = 2,
  533. WOW_GPIO = 3,
  534. };
  535. struct mt76_connac_bss_basic_tlv {
  536. __le16 tag;
  537. __le16 len;
  538. u8 active;
  539. u8 omac_idx;
  540. u8 hw_bss_idx;
  541. u8 band_idx;
  542. __le32 conn_type;
  543. u8 conn_state;
  544. u8 wmm_idx;
  545. u8 bssid[ETH_ALEN];
  546. __le16 bmc_tx_wlan_idx;
  547. __le16 bcn_interval;
  548. u8 dtim_period;
  549. u8 phymode; /* bit(0): A
  550. * bit(1): B
  551. * bit(2): G
  552. * bit(3): GN
  553. * bit(4): AN
  554. * bit(5): AC
  555. */
  556. __le16 sta_idx;
  557. u8 nonht_basic_phy;
  558. u8 pad[3];
  559. } __packed;
  560. struct mt76_connac_bss_qos_tlv {
  561. __le16 tag;
  562. __le16 len;
  563. u8 qos;
  564. u8 pad[3];
  565. } __packed;
  566. struct mt76_connac_beacon_loss_event {
  567. u8 bss_idx;
  568. u8 reason;
  569. u8 pad[2];
  570. } __packed;
  571. struct mt76_connac_mcu_bss_event {
  572. u8 bss_idx;
  573. u8 is_absent;
  574. u8 free_quota;
  575. u8 pad;
  576. } __packed;
  577. struct mt76_connac_mcu_scan_ssid {
  578. __le32 ssid_len;
  579. u8 ssid[IEEE80211_MAX_SSID_LEN];
  580. } __packed;
  581. struct mt76_connac_mcu_scan_channel {
  582. u8 band; /* 1: 2.4GHz
  583. * 2: 5.0GHz
  584. * Others: Reserved
  585. */
  586. u8 channel_num;
  587. } __packed;
  588. struct mt76_connac_mcu_scan_match {
  589. __le32 rssi_th;
  590. u8 ssid[IEEE80211_MAX_SSID_LEN];
  591. u8 ssid_len;
  592. u8 rsv[3];
  593. } __packed;
  594. struct mt76_connac_hw_scan_req {
  595. u8 seq_num;
  596. u8 bss_idx;
  597. u8 scan_type; /* 0: PASSIVE SCAN
  598. * 1: ACTIVE SCAN
  599. */
  600. u8 ssid_type; /* BIT(0) wildcard SSID
  601. * BIT(1) P2P wildcard SSID
  602. * BIT(2) specified SSID + wildcard SSID
  603. * BIT(2) + ssid_type_ext BIT(0) specified SSID only
  604. */
  605. u8 ssids_num;
  606. u8 probe_req_num; /* Number of probe request for each SSID */
  607. u8 scan_func; /* BIT(0) Enable random MAC scan
  608. * BIT(1) Disable DBDC scan type 1~3.
  609. * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan).
  610. */
  611. u8 version; /* 0: Not support fields after ies.
  612. * 1: Support fields after ies.
  613. */
  614. struct mt76_connac_mcu_scan_ssid ssids[4];
  615. __le16 probe_delay_time;
  616. __le16 channel_dwell_time; /* channel Dwell interval */
  617. __le16 timeout_value;
  618. u8 channel_type; /* 0: Full channels
  619. * 1: Only 2.4GHz channels
  620. * 2: Only 5GHz channels
  621. * 3: P2P social channel only (channel #1, #6 and #11)
  622. * 4: Specified channels
  623. * Others: Reserved
  624. */
  625. u8 channels_num; /* valid when channel_type is 4 */
  626. /* valid when channels_num is set */
  627. struct mt76_connac_mcu_scan_channel channels[32];
  628. __le16 ies_len;
  629. u8 ies[MT76_CONNAC_SCAN_IE_LEN];
  630. /* following fields are valid if version > 0 */
  631. u8 ext_channels_num;
  632. u8 ext_ssids_num;
  633. __le16 channel_min_dwell_time;
  634. struct mt76_connac_mcu_scan_channel ext_channels[32];
  635. struct mt76_connac_mcu_scan_ssid ext_ssids[6];
  636. u8 bssid[ETH_ALEN];
  637. u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */
  638. u8 pad[63];
  639. u8 ssid_type_ext;
  640. } __packed;
  641. #define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64
  642. struct mt76_connac_hw_scan_done {
  643. u8 seq_num;
  644. u8 sparse_channel_num;
  645. struct mt76_connac_mcu_scan_channel sparse_channel;
  646. u8 complete_channel_num;
  647. u8 current_state;
  648. u8 version;
  649. u8 pad;
  650. __le32 beacon_scan_num;
  651. u8 pno_enabled;
  652. u8 pad2[3];
  653. u8 sparse_channel_valid_num;
  654. u8 pad3[3];
  655. u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
  656. /* idle format for channel_idle_time
  657. * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms)
  658. * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms)
  659. * 2: dwell time (16us)
  660. */
  661. __le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
  662. /* beacon and probe response count */
  663. u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
  664. u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
  665. __le32 beacon_2g_num;
  666. __le32 beacon_5g_num;
  667. } __packed;
  668. struct mt76_connac_sched_scan_req {
  669. u8 version;
  670. u8 seq_num;
  671. u8 stop_on_match;
  672. u8 ssids_num;
  673. u8 match_num;
  674. u8 pad;
  675. __le16 ie_len;
  676. struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID];
  677. struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH];
  678. u8 channel_type;
  679. u8 channels_num;
  680. u8 intervals_num;
  681. u8 scan_func; /* MT7663: BIT(0) eable random mac address */
  682. struct mt76_connac_mcu_scan_channel channels[64];
  683. __le16 intervals[MT76_CONNAC_MAX_SCHED_SCAN_INTERVAL];
  684. union {
  685. struct {
  686. u8 random_mac[ETH_ALEN];
  687. u8 pad2[58];
  688. } mt7663;
  689. struct {
  690. u8 bss_idx;
  691. u8 pad2[63];
  692. } mt7921;
  693. };
  694. } __packed;
  695. struct mt76_connac_sched_scan_done {
  696. u8 seq_num;
  697. u8 status; /* 0: ssid found */
  698. __le16 pad;
  699. } __packed;
  700. struct bss_info_uni_he {
  701. __le16 tag;
  702. __le16 len;
  703. __le16 he_rts_thres;
  704. u8 he_pe_duration;
  705. u8 su_disable;
  706. __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
  707. u8 rsv[2];
  708. } __packed;
  709. struct mt76_connac_gtk_rekey_tlv {
  710. __le16 tag;
  711. __le16 len;
  712. u8 kek[NL80211_KEK_LEN];
  713. u8 kck[NL80211_KCK_LEN];
  714. u8 replay_ctr[NL80211_REPLAY_CTR_LEN];
  715. u8 rekey_mode; /* 0: rekey offload enable
  716. * 1: rekey offload disable
  717. * 2: rekey update
  718. */
  719. u8 keyid;
  720. u8 pad[2];
  721. __le32 proto; /* WPA-RSN-WAPI-OPSN */
  722. __le32 pairwise_cipher;
  723. __le32 group_cipher;
  724. __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */
  725. __le32 mgmt_group_cipher;
  726. u8 option; /* 1: rekey data update without enabling offload */
  727. u8 reserverd[3];
  728. } __packed;
  729. #define MT76_CONNAC_WOW_MASK_MAX_LEN 16
  730. #define MT76_CONNAC_WOW_PATTEN_MAX_LEN 128
  731. struct mt76_connac_wow_pattern_tlv {
  732. __le16 tag;
  733. __le16 len;
  734. u8 index; /* pattern index */
  735. u8 enable; /* 0: disable
  736. * 1: enable
  737. */
  738. u8 data_len; /* pattern length */
  739. u8 pad;
  740. u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN];
  741. u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN];
  742. u8 rsv[4];
  743. } __packed;
  744. struct mt76_connac_wow_ctrl_tlv {
  745. __le16 tag;
  746. __le16 len;
  747. u8 cmd; /* 0x1: PM_WOWLAN_REQ_START
  748. * 0x2: PM_WOWLAN_REQ_STOP
  749. * 0x3: PM_WOWLAN_PARAM_CLEAR
  750. */
  751. u8 trigger; /* 0: NONE
  752. * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT
  753. * BIT(1): NL80211_WOWLAN_TRIG_ANY
  754. * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT
  755. * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE
  756. * BIT(4): BEACON_LOST
  757. * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT
  758. */
  759. u8 wakeup_hif; /* 0x0: HIF_SDIO
  760. * 0x1: HIF_USB
  761. * 0x2: HIF_PCIE
  762. * 0x3: HIF_GPIO
  763. */
  764. u8 pad;
  765. u8 rsv[4];
  766. } __packed;
  767. struct mt76_connac_wow_gpio_param_tlv {
  768. __le16 tag;
  769. __le16 len;
  770. u8 gpio_pin;
  771. u8 trigger_lvl;
  772. u8 pad[2];
  773. __le32 gpio_interval;
  774. u8 rsv[4];
  775. } __packed;
  776. struct mt76_connac_arpns_tlv {
  777. __le16 tag;
  778. __le16 len;
  779. u8 mode;
  780. u8 ips_num;
  781. u8 option;
  782. u8 pad[1];
  783. } __packed;
  784. struct mt76_connac_suspend_tlv {
  785. __le16 tag;
  786. __le16 len;
  787. u8 enable; /* 0: suspend mode disabled
  788. * 1: suspend mode enabled
  789. */
  790. u8 mdtim; /* LP parameter */
  791. u8 wow_suspend; /* 0: update by origin policy
  792. * 1: update by wow dtim
  793. */
  794. u8 pad[5];
  795. } __packed;
  796. #define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id)
  797. #define to_wcid_hi(id) FIELD_GET(GENMASK(9, 8), (u16)id)
  798. static inline void
  799. mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid,
  800. u8 *wlan_idx_lo, u8 *wlan_idx_hi)
  801. {
  802. *wlan_idx_hi = 0;
  803. if (is_mt7921(dev)) {
  804. *wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0;
  805. *wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0;
  806. } else {
  807. *wlan_idx_lo = wcid ? wcid->idx : 0;
  808. }
  809. }
  810. struct sk_buff *
  811. mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif,
  812. struct mt76_wcid *wcid);
  813. struct wtbl_req_hdr *
  814. mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid,
  815. int cmd, void *sta_wtbl, struct sk_buff **skb);
  816. struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag,
  817. int len, void *sta_ntlv,
  818. void *sta_wtbl);
  819. static inline struct tlv *
  820. mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len)
  821. {
  822. return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL);
  823. }
  824. int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy);
  825. int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif);
  826. void mt76_connac_mcu_sta_basic_tlv(struct sk_buff *skb,
  827. struct ieee80211_vif *vif,
  828. struct ieee80211_sta *sta, bool enable);
  829. void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb,
  830. struct ieee80211_vif *vif,
  831. struct ieee80211_sta *sta, void *sta_wtbl,
  832. void *wtbl_tlv);
  833. void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb,
  834. struct ieee80211_sta *sta,
  835. struct ieee80211_vif *vif);
  836. void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb,
  837. struct ieee80211_sta *sta, void *sta_wtbl,
  838. void *wtbl_tlv);
  839. void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb,
  840. struct ieee80211_ampdu_params *params,
  841. bool enable, bool tx, void *sta_wtbl,
  842. void *wtbl_tlv);
  843. void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb,
  844. struct ieee80211_ampdu_params *params,
  845. bool enable, bool tx);
  846. int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy,
  847. struct ieee80211_vif *vif,
  848. struct mt76_wcid *wcid,
  849. bool enable);
  850. int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
  851. struct ieee80211_ampdu_params *params,
  852. bool enable, bool tx);
  853. int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy,
  854. struct ieee80211_vif *vif,
  855. struct mt76_wcid *wcid,
  856. bool enable);
  857. int mt76_connac_mcu_add_sta_cmd(struct mt76_phy *phy,
  858. struct ieee80211_vif *vif,
  859. struct ieee80211_sta *sta,
  860. struct mt76_wcid *wcid,
  861. bool enable, int cmd);
  862. void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac,
  863. struct ieee80211_vif *vif);
  864. int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band);
  865. int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable,
  866. bool hdr_trans);
  867. int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len,
  868. u32 mode);
  869. int mt76_connac_mcu_start_patch(struct mt76_dev *dev);
  870. int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get);
  871. int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option);
  872. int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif,
  873. struct ieee80211_scan_request *scan_req);
  874. int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy,
  875. struct ieee80211_vif *vif);
  876. int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy,
  877. struct ieee80211_vif *vif,
  878. struct cfg80211_sched_scan_request *sreq);
  879. int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy,
  880. struct ieee80211_vif *vif,
  881. bool enable);
  882. int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw,
  883. struct ieee80211_vif *vif,
  884. struct cfg80211_gtk_rekey_data *key);
  885. int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend);
  886. void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac,
  887. struct ieee80211_vif *vif);
  888. int mt76_connac_mcu_chip_config(struct mt76_dev *dev);
  889. void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb,
  890. struct mt76_connac_coredump *coredump);
  891. #endif /* __MT76_CONNAC_MCU_H */