mt76x02_dfs.h 2.9 KB

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  1. /* SPDX-License-Identifier: ISC */
  2. /*
  3. * Copyright (C) 2016 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
  4. */
  5. #ifndef __MT76x02_DFS_H
  6. #define __MT76x02_DFS_H
  7. #include <linux/types.h>
  8. #include <linux/nl80211.h>
  9. #define MT_DFS_GP_INTERVAL (10 << 4) /* 64 us unit */
  10. #define MT_DFS_NUM_ENGINES 4
  11. /* bbp params */
  12. #define MT_DFS_SYM_ROUND 0
  13. #define MT_DFS_DELTA_DELAY 2
  14. #define MT_DFS_VGA_MASK 0
  15. #define MT_DFS_PWR_GAIN_OFFSET 3
  16. #define MT_DFS_PWR_DOWN_TIME 0xf
  17. #define MT_DFS_RX_PE_MASK 0xff
  18. #define MT_DFS_PKT_END_MASK 0
  19. #define MT_DFS_CH_EN 0xf
  20. /* sw detector params */
  21. #define MT_DFS_EVENT_LOOP 64
  22. #define MT_DFS_SW_TIMEOUT (HZ / 20)
  23. #define MT_DFS_EVENT_WINDOW (HZ / 5)
  24. #define MT_DFS_SEQUENCE_WINDOW (200 * (1 << 20))
  25. #define MT_DFS_EVENT_TIME_MARGIN 2000
  26. #define MT_DFS_PRI_MARGIN 4
  27. #define MT_DFS_SEQUENCE_TH 6
  28. #define MT_DFS_FCC_MAX_PRI ((28570 << 1) + 1000)
  29. #define MT_DFS_FCC_MIN_PRI (3000 - 2)
  30. #define MT_DFS_JP_MAX_PRI ((80000 << 1) + 1000)
  31. #define MT_DFS_JP_MIN_PRI (28500 - 2)
  32. #define MT_DFS_ETSI_MAX_PRI (133333 + 125000 + 117647 + 1000)
  33. #define MT_DFS_ETSI_MIN_PRI (4500 - 20)
  34. struct mt76x02_radar_specs {
  35. u8 mode;
  36. u16 avg_len;
  37. u16 e_low;
  38. u16 e_high;
  39. u16 w_low;
  40. u16 w_high;
  41. u16 w_margin;
  42. u32 t_low;
  43. u32 t_high;
  44. u16 t_margin;
  45. u32 b_low;
  46. u32 b_high;
  47. u32 event_expiration;
  48. u16 pwr_jmp;
  49. };
  50. #define MT_DFS_CHECK_EVENT(x) ((x) != GENMASK(31, 0))
  51. #define MT_DFS_EVENT_ENGINE(x) (((x) & BIT(31)) ? 2 : 0)
  52. #define MT_DFS_EVENT_TIMESTAMP(x) ((x) & GENMASK(21, 0))
  53. #define MT_DFS_EVENT_WIDTH(x) ((x) & GENMASK(11, 0))
  54. struct mt76x02_dfs_event {
  55. unsigned long fetch_ts;
  56. u32 ts;
  57. u16 width;
  58. u8 engine;
  59. };
  60. #define MT_DFS_EVENT_BUFLEN 256
  61. struct mt76x02_dfs_event_rb {
  62. struct mt76x02_dfs_event data[MT_DFS_EVENT_BUFLEN];
  63. int h_rb, t_rb;
  64. };
  65. struct mt76x02_dfs_sequence {
  66. struct list_head head;
  67. u32 first_ts;
  68. u32 last_ts;
  69. u32 pri;
  70. u16 count;
  71. u8 engine;
  72. };
  73. struct mt76x02_dfs_hw_pulse {
  74. u8 engine;
  75. u32 period;
  76. u32 w1;
  77. u32 w2;
  78. u32 burst;
  79. };
  80. struct mt76x02_dfs_sw_detector_params {
  81. u32 min_pri;
  82. u32 max_pri;
  83. u32 pri_margin;
  84. };
  85. struct mt76x02_dfs_engine_stats {
  86. u32 hw_pattern;
  87. u32 hw_pulse_discarded;
  88. u32 sw_pattern;
  89. };
  90. struct mt76x02_dfs_seq_stats {
  91. u32 seq_pool_len;
  92. u32 seq_len;
  93. };
  94. struct mt76x02_dfs_pattern_detector {
  95. u8 chirp_pulse_cnt;
  96. u32 chirp_pulse_ts;
  97. struct mt76x02_dfs_sw_detector_params sw_dpd_params;
  98. struct mt76x02_dfs_event_rb event_rb[2];
  99. struct list_head sequences;
  100. struct list_head seq_pool;
  101. struct mt76x02_dfs_seq_stats seq_stats;
  102. unsigned long last_sw_check;
  103. u32 last_event_ts;
  104. struct mt76x02_dfs_engine_stats stats[MT_DFS_NUM_ENGINES];
  105. struct tasklet_struct dfs_tasklet;
  106. };
  107. void mt76x02_dfs_init_params(struct mt76x02_dev *dev);
  108. void mt76x02_dfs_init_detector(struct mt76x02_dev *dev);
  109. void mt76x02_regd_notifier(struct wiphy *wiphy,
  110. struct regulatory_request *request);
  111. void mt76x02_phy_dfs_adjust_agc(struct mt76x02_dev *dev);
  112. #endif /* __MT76x02_DFS_H */