mt76x02_mac.h 5.8 KB

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  1. /* SPDX-License-Identifier: ISC */
  2. /*
  3. * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
  4. * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
  5. */
  6. #ifndef __MT76X02_MAC_H
  7. #define __MT76X02_MAC_H
  8. struct mt76x02_dev;
  9. struct mt76x02_tx_status {
  10. u8 valid:1;
  11. u8 success:1;
  12. u8 aggr:1;
  13. u8 ack_req:1;
  14. u8 wcid;
  15. u8 pktid;
  16. u8 retry;
  17. u16 rate;
  18. } __packed __aligned(2);
  19. #define MT_VIF_WCID(_n) (254 - ((_n) & 7))
  20. #define MT_MAX_VIFS 8
  21. #define MT_PKTID_RATE GENMASK(4, 0)
  22. #define MT_PKTID_AC GENMASK(6, 5)
  23. struct mt76x02_vif {
  24. struct mt76_wcid group_wcid; /* must be first */
  25. u8 idx;
  26. };
  27. DECLARE_EWMA(pktlen, 8, 8);
  28. struct mt76x02_sta {
  29. struct mt76_wcid wcid; /* must be first */
  30. struct mt76x02_vif *vif;
  31. struct mt76x02_tx_status status;
  32. int n_frames;
  33. struct ewma_pktlen pktlen;
  34. };
  35. #define MT_RXINFO_BA BIT(0)
  36. #define MT_RXINFO_DATA BIT(1)
  37. #define MT_RXINFO_NULL BIT(2)
  38. #define MT_RXINFO_FRAG BIT(3)
  39. #define MT_RXINFO_UNICAST BIT(4)
  40. #define MT_RXINFO_MULTICAST BIT(5)
  41. #define MT_RXINFO_BROADCAST BIT(6)
  42. #define MT_RXINFO_MYBSS BIT(7)
  43. #define MT_RXINFO_CRCERR BIT(8)
  44. #define MT_RXINFO_ICVERR BIT(9)
  45. #define MT_RXINFO_MICERR BIT(10)
  46. #define MT_RXINFO_AMSDU BIT(11)
  47. #define MT_RXINFO_HTC BIT(12)
  48. #define MT_RXINFO_RSSI BIT(13)
  49. #define MT_RXINFO_L2PAD BIT(14)
  50. #define MT_RXINFO_AMPDU BIT(15)
  51. #define MT_RXINFO_DECRYPT BIT(16)
  52. #define MT_RXINFO_BSSIDX3 BIT(17)
  53. #define MT_RXINFO_WAPI_KEY BIT(18)
  54. #define MT_RXINFO_PN_LEN GENMASK(21, 19)
  55. #define MT_RXINFO_SW_FTYPE0 BIT(22)
  56. #define MT_RXINFO_SW_FTYPE1 BIT(23)
  57. #define MT_RXINFO_PROBE_RESP BIT(24)
  58. #define MT_RXINFO_BEACON BIT(25)
  59. #define MT_RXINFO_DISASSOC BIT(26)
  60. #define MT_RXINFO_DEAUTH BIT(27)
  61. #define MT_RXINFO_ACTION BIT(28)
  62. #define MT_RXINFO_TCP_SUM_ERR BIT(30)
  63. #define MT_RXINFO_IP_SUM_ERR BIT(31)
  64. #define MT_RXWI_CTL_WCID GENMASK(7, 0)
  65. #define MT_RXWI_CTL_KEY_IDX GENMASK(9, 8)
  66. #define MT_RXWI_CTL_BSS_IDX GENMASK(12, 10)
  67. #define MT_RXWI_CTL_UDF GENMASK(15, 13)
  68. #define MT_RXWI_CTL_MPDU_LEN GENMASK(29, 16)
  69. #define MT_RXWI_CTL_EOF BIT(31)
  70. #define MT_RXWI_TID GENMASK(3, 0)
  71. #define MT_RXWI_SN GENMASK(15, 4)
  72. #define MT_RXWI_RATE_INDEX GENMASK(5, 0)
  73. #define MT_RXWI_RATE_LDPC BIT(6)
  74. #define MT_RXWI_RATE_BW GENMASK(8, 7)
  75. #define MT_RXWI_RATE_SGI BIT(9)
  76. #define MT_RXWI_RATE_STBC BIT(10)
  77. #define MT_RXWI_RATE_LDPC_EXSYM BIT(11)
  78. #define MT_RXWI_RATE_PHY GENMASK(15, 13)
  79. #define MT_RATE_INDEX_VHT_IDX GENMASK(3, 0)
  80. #define MT_RATE_INDEX_VHT_NSS GENMASK(5, 4)
  81. struct mt76x02_rxwi {
  82. __le32 rxinfo;
  83. __le32 ctl;
  84. __le16 tid_sn;
  85. __le16 rate;
  86. u8 rssi[4];
  87. __le32 bbp_rxinfo[4];
  88. };
  89. #define MT_TX_PWR_ADJ GENMASK(3, 0)
  90. enum mt76x2_phy_bandwidth {
  91. MT_PHY_BW_20,
  92. MT_PHY_BW_40,
  93. MT_PHY_BW_80,
  94. };
  95. #define MT_TXWI_FLAGS_FRAG BIT(0)
  96. #define MT_TXWI_FLAGS_MMPS BIT(1)
  97. #define MT_TXWI_FLAGS_CFACK BIT(2)
  98. #define MT_TXWI_FLAGS_TS BIT(3)
  99. #define MT_TXWI_FLAGS_AMPDU BIT(4)
  100. #define MT_TXWI_FLAGS_MPDU_DENSITY GENMASK(7, 5)
  101. #define MT_TXWI_FLAGS_TXOP GENMASK(9, 8)
  102. #define MT_TXWI_FLAGS_NDPS BIT(10)
  103. #define MT_TXWI_FLAGS_RTSBWSIG BIT(11)
  104. #define MT_TXWI_FLAGS_NDP_BW GENMASK(13, 12)
  105. #define MT_TXWI_FLAGS_SOUND BIT(14)
  106. #define MT_TXWI_FLAGS_TX_RATE_LUT BIT(15)
  107. #define MT_TXWI_ACK_CTL_REQ BIT(0)
  108. #define MT_TXWI_ACK_CTL_NSEQ BIT(1)
  109. #define MT_TXWI_ACK_CTL_BA_WINDOW GENMASK(7, 2)
  110. struct mt76x02_txwi {
  111. __le16 flags;
  112. __le16 rate;
  113. u8 ack_ctl;
  114. u8 wcid;
  115. __le16 len_ctl;
  116. __le32 iv;
  117. __le32 eiv;
  118. u8 aid;
  119. u8 txstream;
  120. u8 ctl2;
  121. u8 pktid;
  122. } __packed __aligned(4);
  123. static inline bool mt76x02_wait_for_mac(struct mt76_dev *dev)
  124. {
  125. const u32 MAC_CSR0 = 0x1000;
  126. int i;
  127. for (i = 0; i < 500; i++) {
  128. if (test_bit(MT76_REMOVED, &dev->phy.state))
  129. return false;
  130. switch (dev->bus->rr(dev, MAC_CSR0)) {
  131. case 0:
  132. case ~0:
  133. break;
  134. default:
  135. return true;
  136. }
  137. usleep_range(5000, 10000);
  138. }
  139. return false;
  140. }
  141. void mt76x02_mac_reset_counters(struct mt76x02_dev *dev);
  142. void mt76x02_mac_set_short_preamble(struct mt76x02_dev *dev, bool enable);
  143. int mt76x02_mac_shared_key_setup(struct mt76x02_dev *dev, u8 vif_idx,
  144. u8 key_idx, struct ieee80211_key_conf *key);
  145. int mt76x02_mac_wcid_set_key(struct mt76x02_dev *dev, u8 idx,
  146. struct ieee80211_key_conf *key);
  147. void mt76x02_mac_wcid_sync_pn(struct mt76x02_dev *dev, u8 idx,
  148. struct ieee80211_key_conf *key);
  149. void mt76x02_mac_wcid_setup(struct mt76x02_dev *dev, u8 idx, u8 vif_idx,
  150. u8 *mac);
  151. void mt76x02_mac_wcid_set_drop(struct mt76x02_dev *dev, u8 idx, bool drop);
  152. void mt76x02_mac_wcid_set_rate(struct mt76x02_dev *dev, struct mt76_wcid *wcid,
  153. const struct ieee80211_tx_rate *rate);
  154. bool mt76x02_mac_load_tx_status(struct mt76x02_dev *dev,
  155. struct mt76x02_tx_status *stat);
  156. void mt76x02_send_tx_status(struct mt76x02_dev *dev,
  157. struct mt76x02_tx_status *stat, u8 *update);
  158. int mt76x02_mac_process_rx(struct mt76x02_dev *dev, struct sk_buff *skb,
  159. void *rxi);
  160. void mt76x02_mac_set_tx_protection(struct mt76x02_dev *dev, bool legacy_prot,
  161. int ht_mode);
  162. void mt76x02_mac_set_rts_thresh(struct mt76x02_dev *dev, u32 val);
  163. void mt76x02_mac_setaddr(struct mt76x02_dev *dev, const u8 *addr);
  164. void mt76x02_mac_write_txwi(struct mt76x02_dev *dev, struct mt76x02_txwi *txwi,
  165. struct sk_buff *skb, struct mt76_wcid *wcid,
  166. struct ieee80211_sta *sta, int len);
  167. void mt76x02_mac_poll_tx_status(struct mt76x02_dev *dev, bool irq);
  168. void mt76x02_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e);
  169. void mt76x02_update_channel(struct mt76_dev *mdev);
  170. void mt76x02_mac_work(struct work_struct *work);
  171. void mt76x02_mac_cc_reset(struct mt76x02_dev *dev);
  172. void mt76x02_mac_set_bssid(struct mt76x02_dev *dev, u8 idx, const u8 *addr);
  173. void mt76x02_mac_set_beacon(struct mt76x02_dev *dev, struct sk_buff *skb);
  174. void mt76x02_mac_set_beacon_enable(struct mt76x02_dev *dev,
  175. struct ieee80211_vif *vif, bool enable);
  176. void mt76x02_edcca_init(struct mt76x02_dev *dev);
  177. #endif