mt76x02_phy.c 5.0 KB

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  1. // SPDX-License-Identifier: ISC
  2. /*
  3. * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
  4. * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
  5. */
  6. #include <linux/kernel.h>
  7. #include "mt76x02.h"
  8. #include "mt76x02_phy.h"
  9. void mt76x02_phy_set_rxpath(struct mt76x02_dev *dev)
  10. {
  11. u32 val;
  12. val = mt76_rr(dev, MT_BBP(AGC, 0));
  13. val &= ~BIT(4);
  14. switch (dev->mphy.chainmask & 0xf) {
  15. case 2:
  16. val |= BIT(3);
  17. break;
  18. default:
  19. val &= ~BIT(3);
  20. break;
  21. }
  22. mt76_wr(dev, MT_BBP(AGC, 0), val);
  23. mb();
  24. val = mt76_rr(dev, MT_BBP(AGC, 0));
  25. }
  26. EXPORT_SYMBOL_GPL(mt76x02_phy_set_rxpath);
  27. void mt76x02_phy_set_txdac(struct mt76x02_dev *dev)
  28. {
  29. int txpath;
  30. txpath = (dev->mphy.chainmask >> 8) & 0xf;
  31. switch (txpath) {
  32. case 2:
  33. mt76_set(dev, MT_BBP(TXBE, 5), 0x3);
  34. break;
  35. default:
  36. mt76_clear(dev, MT_BBP(TXBE, 5), 0x3);
  37. break;
  38. }
  39. }
  40. EXPORT_SYMBOL_GPL(mt76x02_phy_set_txdac);
  41. static u32
  42. mt76x02_tx_power_mask(u8 v1, u8 v2, u8 v3, u8 v4)
  43. {
  44. u32 val = 0;
  45. val |= (v1 & (BIT(6) - 1)) << 0;
  46. val |= (v2 & (BIT(6) - 1)) << 8;
  47. val |= (v3 & (BIT(6) - 1)) << 16;
  48. val |= (v4 & (BIT(6) - 1)) << 24;
  49. return val;
  50. }
  51. int mt76x02_get_max_rate_power(struct mt76_rate_power *r)
  52. {
  53. s8 ret = 0;
  54. int i;
  55. for (i = 0; i < sizeof(r->all); i++)
  56. ret = max(ret, r->all[i]);
  57. return ret;
  58. }
  59. EXPORT_SYMBOL_GPL(mt76x02_get_max_rate_power);
  60. void mt76x02_limit_rate_power(struct mt76_rate_power *r, int limit)
  61. {
  62. int i;
  63. for (i = 0; i < sizeof(r->all); i++)
  64. if (r->all[i] > limit)
  65. r->all[i] = limit;
  66. }
  67. EXPORT_SYMBOL_GPL(mt76x02_limit_rate_power);
  68. void mt76x02_add_rate_power_offset(struct mt76_rate_power *r, int offset)
  69. {
  70. int i;
  71. for (i = 0; i < sizeof(r->all); i++)
  72. r->all[i] += offset;
  73. }
  74. EXPORT_SYMBOL_GPL(mt76x02_add_rate_power_offset);
  75. void mt76x02_phy_set_txpower(struct mt76x02_dev *dev, int txp_0, int txp_1)
  76. {
  77. struct mt76_rate_power *t = &dev->mt76.rate_power;
  78. mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_0, txp_0);
  79. mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_1, txp_1);
  80. mt76_wr(dev, MT_TX_PWR_CFG_0,
  81. mt76x02_tx_power_mask(t->cck[0], t->cck[2], t->ofdm[0],
  82. t->ofdm[2]));
  83. mt76_wr(dev, MT_TX_PWR_CFG_1,
  84. mt76x02_tx_power_mask(t->ofdm[4], t->ofdm[6], t->ht[0],
  85. t->ht[2]));
  86. mt76_wr(dev, MT_TX_PWR_CFG_2,
  87. mt76x02_tx_power_mask(t->ht[4], t->ht[6], t->ht[8],
  88. t->ht[10]));
  89. mt76_wr(dev, MT_TX_PWR_CFG_3,
  90. mt76x02_tx_power_mask(t->ht[12], t->ht[14], t->stbc[0],
  91. t->stbc[2]));
  92. mt76_wr(dev, MT_TX_PWR_CFG_4,
  93. mt76x02_tx_power_mask(t->stbc[4], t->stbc[6], 0, 0));
  94. mt76_wr(dev, MT_TX_PWR_CFG_7,
  95. mt76x02_tx_power_mask(t->ofdm[7], t->vht[8], t->ht[7],
  96. t->vht[9]));
  97. mt76_wr(dev, MT_TX_PWR_CFG_8,
  98. mt76x02_tx_power_mask(t->ht[14], 0, t->vht[8], t->vht[9]));
  99. mt76_wr(dev, MT_TX_PWR_CFG_9,
  100. mt76x02_tx_power_mask(t->ht[7], 0, t->stbc[8], t->stbc[9]));
  101. }
  102. EXPORT_SYMBOL_GPL(mt76x02_phy_set_txpower);
  103. void mt76x02_phy_set_bw(struct mt76x02_dev *dev, int width, u8 ctrl)
  104. {
  105. int core_val, agc_val;
  106. switch (width) {
  107. case NL80211_CHAN_WIDTH_80:
  108. core_val = 3;
  109. agc_val = 7;
  110. break;
  111. case NL80211_CHAN_WIDTH_40:
  112. core_val = 2;
  113. agc_val = 3;
  114. break;
  115. default:
  116. core_val = 0;
  117. agc_val = 1;
  118. break;
  119. }
  120. mt76_rmw_field(dev, MT_BBP(CORE, 1), MT_BBP_CORE_R1_BW, core_val);
  121. mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_BW, agc_val);
  122. mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_CTRL_CHAN, ctrl);
  123. mt76_rmw_field(dev, MT_BBP(TXBE, 0), MT_BBP_TXBE_R0_CTRL_CHAN, ctrl);
  124. }
  125. EXPORT_SYMBOL_GPL(mt76x02_phy_set_bw);
  126. void mt76x02_phy_set_band(struct mt76x02_dev *dev, int band,
  127. bool primary_upper)
  128. {
  129. switch (band) {
  130. case NL80211_BAND_2GHZ:
  131. mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
  132. mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
  133. break;
  134. case NL80211_BAND_5GHZ:
  135. mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
  136. mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
  137. break;
  138. }
  139. mt76_rmw_field(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_UPPER_40M,
  140. primary_upper);
  141. }
  142. EXPORT_SYMBOL_GPL(mt76x02_phy_set_band);
  143. bool mt76x02_phy_adjust_vga_gain(struct mt76x02_dev *dev)
  144. {
  145. u8 limit = dev->cal.low_gain > 0 ? 16 : 4;
  146. bool ret = false;
  147. u32 false_cca;
  148. false_cca = FIELD_GET(MT_RX_STAT_1_CCA_ERRORS,
  149. mt76_rr(dev, MT_RX_STAT_1));
  150. dev->cal.false_cca = false_cca;
  151. if (false_cca > 800 && dev->cal.agc_gain_adjust < limit) {
  152. dev->cal.agc_gain_adjust += 2;
  153. ret = true;
  154. } else if ((false_cca < 10 && dev->cal.agc_gain_adjust > 0) ||
  155. (dev->cal.agc_gain_adjust >= limit && false_cca < 500)) {
  156. dev->cal.agc_gain_adjust -= 2;
  157. ret = true;
  158. }
  159. dev->cal.agc_lowest_gain = dev->cal.agc_gain_adjust >= limit;
  160. return ret;
  161. }
  162. EXPORT_SYMBOL_GPL(mt76x02_phy_adjust_vga_gain);
  163. void mt76x02_init_agc_gain(struct mt76x02_dev *dev)
  164. {
  165. dev->cal.agc_gain_init[0] = mt76_get_field(dev, MT_BBP(AGC, 8),
  166. MT_BBP_AGC_GAIN);
  167. dev->cal.agc_gain_init[1] = mt76_get_field(dev, MT_BBP(AGC, 9),
  168. MT_BBP_AGC_GAIN);
  169. memcpy(dev->cal.agc_gain_cur, dev->cal.agc_gain_init,
  170. sizeof(dev->cal.agc_gain_cur));
  171. dev->cal.low_gain = -1;
  172. dev->cal.gain_init_done = true;
  173. }
  174. EXPORT_SYMBOL_GPL(mt76x02_init_agc_gain);