mt76x02_regs.h 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706
  1. /* SPDX-License-Identifier: ISC */
  2. /*
  3. * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
  4. */
  5. #ifndef __MT76X02_REGS_H
  6. #define __MT76X02_REGS_H
  7. #define MT_ASIC_VERSION 0x0000
  8. #define MT76XX_REV_E3 0x22
  9. #define MT76XX_REV_E4 0x33
  10. #define MT_CMB_CTRL 0x0020
  11. #define MT_CMB_CTRL_XTAL_RDY BIT(22)
  12. #define MT_CMB_CTRL_PLL_LD BIT(23)
  13. #define MT_EFUSE_CTRL 0x0024
  14. #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
  15. #define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
  16. #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
  17. #define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)
  18. #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
  19. #define MT_EFUSE_CTRL_KICK BIT(30)
  20. #define MT_EFUSE_CTRL_SEL BIT(31)
  21. #define MT_EFUSE_DATA_BASE 0x0028
  22. #define MT_EFUSE_DATA(_n) (MT_EFUSE_DATA_BASE + ((_n) << 2))
  23. #define MT_COEXCFG0 0x0040
  24. #define MT_COEXCFG0_COEX_EN BIT(0)
  25. #define MT_WLAN_FUN_CTRL 0x0080
  26. #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
  27. #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
  28. #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
  29. #define MT_COEXCFG3 0x004c
  30. #define MT_LDO_CTRL_0 0x006c
  31. #define MT_LDO_CTRL_1 0x0070
  32. #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */
  33. #define MT_WLAN_FUN_CTRL_CSR_F20M_CKEN BIT(3) /* MT76x2 */
  34. #define MT_WLAN_FUN_CTRL_PCIE_CLK_REQ BIT(4)
  35. #define MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL BIT(5)
  36. #define MT_WLAN_FUN_CTRL_INV_ANT_SEL BIT(6)
  37. #define MT_WLAN_FUN_CTRL_WAKE_HOST BIT(7)
  38. #define MT_WLAN_FUN_CTRL_THERM_RST BIT(8) /* MT76x2 */
  39. #define MT_WLAN_FUN_CTRL_THERM_CKEN BIT(9) /* MT76x2 */
  40. #define MT_WLAN_FUN_CTRL_GPIO_IN GENMASK(15, 8) /* MT76x0 */
  41. #define MT_WLAN_FUN_CTRL_GPIO_OUT GENMASK(23, 16) /* MT76x0 */
  42. #define MT_WLAN_FUN_CTRL_GPIO_OUT_EN GENMASK(31, 24) /* MT76x0 */
  43. /* MT76x0 */
  44. #define MT_CSR_EE_CFG1 0x0104
  45. #define MT_XO_CTRL0 0x0100
  46. #define MT_XO_CTRL1 0x0104
  47. #define MT_XO_CTRL2 0x0108
  48. #define MT_XO_CTRL3 0x010c
  49. #define MT_XO_CTRL4 0x0110
  50. #define MT_XO_CTRL5 0x0114
  51. #define MT_XO_CTRL5_C2_VAL GENMASK(14, 8)
  52. #define MT_XO_CTRL6 0x0118
  53. #define MT_XO_CTRL6_C2_CTRL GENMASK(14, 8)
  54. #define MT_XO_CTRL7 0x011c
  55. #define MT_IOCFG_6 0x0124
  56. #define MT_USB_U3DMA_CFG 0x9018
  57. #define MT_USB_DMA_CFG_RX_BULK_AGG_TOUT GENMASK(7, 0)
  58. #define MT_USB_DMA_CFG_RX_BULK_AGG_LMT GENMASK(15, 8)
  59. #define MT_USB_DMA_CFG_UDMA_TX_WL_DROP BIT(16)
  60. #define MT_USB_DMA_CFG_WAKE_UP_EN BIT(17)
  61. #define MT_USB_DMA_CFG_RX_DROP_OR_PAD BIT(18)
  62. #define MT_USB_DMA_CFG_TX_CLR BIT(19)
  63. #define MT_USB_DMA_CFG_TXOP_HALT BIT(20)
  64. #define MT_USB_DMA_CFG_RX_BULK_AGG_EN BIT(21)
  65. #define MT_USB_DMA_CFG_RX_BULK_EN BIT(22)
  66. #define MT_USB_DMA_CFG_TX_BULK_EN BIT(23)
  67. #define MT_USB_DMA_CFG_EP_OUT_VALID GENMASK(29, 24)
  68. #define MT_USB_DMA_CFG_RX_BUSY BIT(30)
  69. #define MT_USB_DMA_CFG_TX_BUSY BIT(31)
  70. #define MT_WLAN_MTC_CTRL 0x10148
  71. #define MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP BIT(0)
  72. #define MT_WLAN_MTC_CTRL_PWR_ACK BIT(12)
  73. #define MT_WLAN_MTC_CTRL_PWR_ACK_S BIT(13)
  74. #define MT_WLAN_MTC_CTRL_BBP_MEM_PD GENMASK(19, 16)
  75. #define MT_WLAN_MTC_CTRL_PBF_MEM_PD BIT(20)
  76. #define MT_WLAN_MTC_CTRL_FCE_MEM_PD BIT(21)
  77. #define MT_WLAN_MTC_CTRL_TSO_MEM_PD BIT(22)
  78. #define MT_WLAN_MTC_CTRL_BBP_MEM_RB BIT(24)
  79. #define MT_WLAN_MTC_CTRL_PBF_MEM_RB BIT(25)
  80. #define MT_WLAN_MTC_CTRL_FCE_MEM_RB BIT(26)
  81. #define MT_WLAN_MTC_CTRL_TSO_MEM_RB BIT(27)
  82. #define MT_WLAN_MTC_CTRL_STATE_UP BIT(28)
  83. #define MT_INT_SOURCE_CSR 0x0200
  84. #define MT_INT_MASK_CSR 0x0204
  85. #define MT_INT_RX_DONE(_n) BIT(_n)
  86. #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
  87. #define MT_INT_TX_DONE_ALL GENMASK(13, 4)
  88. #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
  89. #define MT_INT_RX_COHERENT BIT(16)
  90. #define MT_INT_TX_COHERENT BIT(17)
  91. #define MT_INT_ANY_COHERENT BIT(18)
  92. #define MT_INT_MCU_CMD BIT(19)
  93. #define MT_INT_TBTT BIT(20)
  94. #define MT_INT_PRE_TBTT BIT(21)
  95. #define MT_INT_TX_STAT BIT(22)
  96. #define MT_INT_AUTO_WAKEUP BIT(23)
  97. #define MT_INT_GPTIMER BIT(24)
  98. #define MT_INT_RXDELAYINT BIT(26)
  99. #define MT_INT_TXDELAYINT BIT(27)
  100. #define MT_WPDMA_GLO_CFG 0x0208
  101. #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
  102. #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
  103. #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
  104. #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3)
  105. #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)
  106. #define MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE BIT(6)
  107. #define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7)
  108. #define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8)
  109. #define MT_WPDMA_GLO_CFG_CLK_GATE_DIS BIT(30)
  110. #define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31)
  111. #define MT_WPDMA_RST_IDX 0x020c
  112. #define MT_WPDMA_DELAY_INT_CFG 0x0210
  113. #define MT_WMM_AIFSN 0x0214
  114. #define MT_WMM_AIFSN_MASK GENMASK(3, 0)
  115. #define MT_WMM_AIFSN_SHIFT(_n) ((_n) * 4)
  116. #define MT_WMM_CWMIN 0x0218
  117. #define MT_WMM_CWMIN_MASK GENMASK(3, 0)
  118. #define MT_WMM_CWMIN_SHIFT(_n) ((_n) * 4)
  119. #define MT_WMM_CWMAX 0x021c
  120. #define MT_WMM_CWMAX_MASK GENMASK(3, 0)
  121. #define MT_WMM_CWMAX_SHIFT(_n) ((_n) * 4)
  122. #define MT_WMM_TXOP_BASE 0x0220
  123. #define MT_WMM_TXOP(_n) (MT_WMM_TXOP_BASE + (((_n) / 2) << 2))
  124. #define MT_WMM_TXOP_SHIFT(_n) (((_n) & 1) * 16)
  125. #define MT_WMM_TXOP_MASK GENMASK(15, 0)
  126. #define MT_WMM_CTRL 0x0230 /* MT76x0 */
  127. #define MT_FCE_DMA_ADDR 0x0230
  128. #define MT_FCE_DMA_LEN 0x0234
  129. #define MT_USB_DMA_CFG 0x0238
  130. #define MT_TSO_CTRL 0x0250
  131. #define MT_HEADER_TRANS_CTRL_REG 0x0260
  132. #define MT_US_CYC_CFG 0x02a4
  133. #define MT_US_CYC_CNT GENMASK(7, 0)
  134. #define MT_TX_RING_BASE 0x0300
  135. #define MT_RX_RING_BASE 0x03c0
  136. #define MT_TX_HW_QUEUE_MCU 8
  137. #define MT_TX_HW_QUEUE_MGMT 9
  138. #define MT_PBF_SYS_CTRL 0x0400
  139. #define MT_PBF_SYS_CTRL_MCU_RESET BIT(0)
  140. #define MT_PBF_SYS_CTRL_DMA_RESET BIT(1)
  141. #define MT_PBF_SYS_CTRL_MAC_RESET BIT(2)
  142. #define MT_PBF_SYS_CTRL_PBF_RESET BIT(3)
  143. #define MT_PBF_SYS_CTRL_ASY_RESET BIT(4)
  144. #define MT_PBF_CFG 0x0404
  145. #define MT_PBF_CFG_TX0Q_EN BIT(0)
  146. #define MT_PBF_CFG_TX1Q_EN BIT(1)
  147. #define MT_PBF_CFG_TX2Q_EN BIT(2)
  148. #define MT_PBF_CFG_TX3Q_EN BIT(3)
  149. #define MT_PBF_CFG_RX0Q_EN BIT(4)
  150. #define MT_PBF_CFG_RX_DROP_EN BIT(8)
  151. #define MT_PBF_TX_MAX_PCNT 0x0408
  152. #define MT_PBF_RX_MAX_PCNT 0x040c
  153. #define MT_BCN_OFFSET_BASE 0x041c
  154. #define MT_BCN_OFFSET(_n) (MT_BCN_OFFSET_BASE + ((_n) << 2))
  155. #define MT_RXQ_STA 0x0430
  156. #define MT_TXQ_STA 0x0434
  157. #define MT_RF_CSR_CFG 0x0500
  158. #define MT_RF_CSR_CFG_DATA GENMASK(7, 0)
  159. #define MT_RF_CSR_CFG_REG_ID GENMASK(14, 8)
  160. #define MT_RF_CSR_CFG_REG_BANK GENMASK(17, 15)
  161. #define MT_RF_CSR_CFG_WR BIT(30)
  162. #define MT_RF_CSR_CFG_KICK BIT(31)
  163. #define MT_RF_BYPASS_0 0x0504
  164. #define MT_RF_BYPASS_1 0x0508
  165. #define MT_RF_SETTING_0 0x050c
  166. #define MT_RF_MISC 0x0518
  167. #define MT_RF_DATA_WRITE 0x0524
  168. #define MT_RF_CTRL 0x0528
  169. #define MT_RF_CTRL_ADDR GENMASK(11, 0)
  170. #define MT_RF_CTRL_WRITE BIT(12)
  171. #define MT_RF_CTRL_BUSY BIT(13)
  172. #define MT_RF_CTRL_IDX BIT(16)
  173. #define MT_RF_DATA_READ 0x052c
  174. #define MT_COM_REG0 0x0730
  175. #define MT_COM_REG1 0x0734
  176. #define MT_COM_REG2 0x0738
  177. #define MT_COM_REG3 0x073C
  178. #define MT_LED_CTRL 0x0770
  179. #define MT_LED_CTRL_REPLAY(_n) BIT(0 + (8 * (_n)))
  180. #define MT_LED_CTRL_POLARITY(_n) BIT(1 + (8 * (_n)))
  181. #define MT_LED_CTRL_TX_BLINK_MODE(_n) BIT(2 + (8 * (_n)))
  182. #define MT_LED_CTRL_KICK(_n) BIT(7 + (8 * (_n)))
  183. #define MT_LED_TX_BLINK_0 0x0774
  184. #define MT_LED_TX_BLINK_1 0x0778
  185. #define MT_LED_S0_BASE 0x077C
  186. #define MT_LED_S0(_n) (MT_LED_S0_BASE + 8 * (_n))
  187. #define MT_LED_S1_BASE 0x0780
  188. #define MT_LED_S1(_n) (MT_LED_S1_BASE + 8 * (_n))
  189. #define MT_LED_STATUS_OFF GENMASK(31, 24)
  190. #define MT_LED_STATUS_ON GENMASK(23, 16)
  191. #define MT_LED_STATUS_DURATION GENMASK(15, 8)
  192. #define MT_FCE_PSE_CTRL 0x0800
  193. #define MT_FCE_PARAMETERS 0x0804
  194. #define MT_FCE_CSO 0x0808
  195. #define MT_FCE_L2_STUFF 0x080c
  196. #define MT_FCE_L2_STUFF_HT_L2_EN BIT(0)
  197. #define MT_FCE_L2_STUFF_QOS_L2_EN BIT(1)
  198. #define MT_FCE_L2_STUFF_RX_STUFF_EN BIT(2)
  199. #define MT_FCE_L2_STUFF_TX_STUFF_EN BIT(3)
  200. #define MT_FCE_L2_STUFF_WR_MPDU_LEN_EN BIT(4)
  201. #define MT_FCE_L2_STUFF_MVINV_BSWAP BIT(5)
  202. #define MT_FCE_L2_STUFF_TS_CMD_QSEL_EN GENMASK(15, 8)
  203. #define MT_FCE_L2_STUFF_TS_LEN_EN GENMASK(23, 16)
  204. #define MT_FCE_L2_STUFF_OTHER_PORT GENMASK(25, 24)
  205. #define MT_FCE_WLAN_FLOW_CONTROL1 0x0824
  206. #define MT_TX_CPU_FROM_FCE_BASE_PTR 0x09a0
  207. #define MT_TX_CPU_FROM_FCE_MAX_COUNT 0x09a4
  208. #define MT_TX_CPU_FROM_FCE_CPU_DESC_IDX 0x09a8
  209. #define MT_FCE_PDMA_GLOBAL_CONF 0x09c4
  210. #define MT_FCE_SKIP_FS 0x0a6c
  211. #define MT_PAUSE_ENABLE_CONTROL1 0x0a38
  212. #define MT_MAC_CSR0 0x1000
  213. #define MT_MAC_SYS_CTRL 0x1004
  214. #define MT_MAC_SYS_CTRL_RESET_CSR BIT(0)
  215. #define MT_MAC_SYS_CTRL_RESET_BBP BIT(1)
  216. #define MT_MAC_SYS_CTRL_ENABLE_TX BIT(2)
  217. #define MT_MAC_SYS_CTRL_ENABLE_RX BIT(3)
  218. #define MT_MAC_ADDR_DW0 0x1008
  219. #define MT_MAC_ADDR_DW1 0x100c
  220. #define MT_MAC_ADDR_DW1_U2ME_MASK GENMASK(23, 16)
  221. #define MT_MAC_BSSID_DW0 0x1010
  222. #define MT_MAC_BSSID_DW1 0x1014
  223. #define MT_MAC_BSSID_DW1_ADDR GENMASK(15, 0)
  224. #define MT_MAC_BSSID_DW1_MBSS_MODE GENMASK(17, 16)
  225. #define MT_MAC_BSSID_DW1_MBEACON_N GENMASK(20, 18)
  226. #define MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT BIT(21)
  227. #define MT_MAC_BSSID_DW1_MBSS_MODE_B2 BIT(22)
  228. #define MT_MAC_BSSID_DW1_MBEACON_N_B3 BIT(23)
  229. #define MT_MAC_BSSID_DW1_MBSS_IDX_BYTE GENMASK(26, 24)
  230. #define MT_MAX_LEN_CFG 0x1018
  231. #define MT_MAX_LEN_CFG_AMPDU GENMASK(13, 12)
  232. #define MT_LED_CFG 0x102c
  233. #define MT_AMPDU_MAX_LEN_20M1S 0x1030
  234. #define MT_AMPDU_MAX_LEN_20M2S 0x1034
  235. #define MT_AMPDU_MAX_LEN_40M1S 0x1038
  236. #define MT_AMPDU_MAX_LEN_40M2S 0x103c
  237. #define MT_AMPDU_MAX_LEN 0x1040
  238. #define MT_WCID_DROP_BASE 0x106c
  239. #define MT_WCID_DROP(_n) (MT_WCID_DROP_BASE + ((_n) >> 5) * 4)
  240. #define MT_WCID_DROP_MASK(_n) BIT((_n) % 32)
  241. #define MT_BCN_BYPASS_MASK 0x108c
  242. #define MT_MAC_APC_BSSID_BASE 0x1090
  243. #define MT_MAC_APC_BSSID_L(_n) (MT_MAC_APC_BSSID_BASE + ((_n) * 8))
  244. #define MT_MAC_APC_BSSID_H(_n) (MT_MAC_APC_BSSID_BASE + ((_n) * 8 + 4))
  245. #define MT_MAC_APC_BSSID_H_ADDR GENMASK(15, 0)
  246. #define MT_MAC_APC_BSSID0_H_EN BIT(16)
  247. #define MT_XIFS_TIME_CFG 0x1100
  248. #define MT_XIFS_TIME_CFG_CCK_SIFS GENMASK(7, 0)
  249. #define MT_XIFS_TIME_CFG_OFDM_SIFS GENMASK(15, 8)
  250. #define MT_XIFS_TIME_CFG_OFDM_XIFS GENMASK(19, 16)
  251. #define MT_XIFS_TIME_CFG_EIFS GENMASK(28, 20)
  252. #define MT_XIFS_TIME_CFG_BB_RXEND_EN BIT(29)
  253. #define MT_BKOFF_SLOT_CFG 0x1104
  254. #define MT_BKOFF_SLOT_CFG_SLOTTIME GENMASK(7, 0)
  255. #define MT_BKOFF_SLOT_CFG_CC_DELAY GENMASK(11, 8)
  256. #define MT_CH_TIME_CFG 0x110c
  257. #define MT_CH_TIME_CFG_TIMER_EN BIT(0)
  258. #define MT_CH_TIME_CFG_TX_AS_BUSY BIT(1)
  259. #define MT_CH_TIME_CFG_RX_AS_BUSY BIT(2)
  260. #define MT_CH_TIME_CFG_NAV_AS_BUSY BIT(3)
  261. #define MT_CH_TIME_CFG_EIFS_AS_BUSY BIT(4)
  262. #define MT_CH_TIME_CFG_MDRDY_CNT_EN BIT(5)
  263. #define MT_CH_CCA_RC_EN BIT(6)
  264. #define MT_CH_TIME_CFG_CH_TIMER_CLR GENMASK(9, 8)
  265. #define MT_CH_TIME_CFG_MDRDY_CLR GENMASK(11, 10)
  266. #define MT_PBF_LIFE_TIMER 0x1110
  267. #define MT_BEACON_TIME_CFG 0x1114
  268. #define MT_BEACON_TIME_CFG_INTVAL GENMASK(15, 0)
  269. #define MT_BEACON_TIME_CFG_TIMER_EN BIT(16)
  270. #define MT_BEACON_TIME_CFG_SYNC_MODE GENMASK(18, 17)
  271. #define MT_BEACON_TIME_CFG_TBTT_EN BIT(19)
  272. #define MT_BEACON_TIME_CFG_BEACON_TX BIT(20)
  273. #define MT_BEACON_TIME_CFG_TSF_COMP GENMASK(31, 24)
  274. #define MT_TBTT_SYNC_CFG 0x1118
  275. #define MT_TSF_TIMER_DW0 0x111c
  276. #define MT_TSF_TIMER_DW1 0x1120
  277. #define MT_TBTT_TIMER 0x1124
  278. #define MT_TBTT_TIMER_VAL GENMASK(16, 0)
  279. #define MT_INT_TIMER_CFG 0x1128
  280. #define MT_INT_TIMER_CFG_PRE_TBTT GENMASK(15, 0)
  281. #define MT_INT_TIMER_CFG_GP_TIMER GENMASK(31, 16)
  282. #define MT_INT_TIMER_EN 0x112c
  283. #define MT_INT_TIMER_EN_PRE_TBTT_EN BIT(0)
  284. #define MT_INT_TIMER_EN_GP_TIMER_EN BIT(1)
  285. #define MT_CH_IDLE 0x1130
  286. #define MT_CH_BUSY 0x1134
  287. #define MT_EXT_CH_BUSY 0x1138
  288. #define MT_ED_CCA_TIMER 0x1140
  289. #define MT_MAC_STATUS 0x1200
  290. #define MT_MAC_STATUS_TX BIT(0)
  291. #define MT_MAC_STATUS_RX BIT(1)
  292. #define MT_PWR_PIN_CFG 0x1204
  293. #define MT_AUX_CLK_CFG 0x120c
  294. #define MT_BB_PA_MODE_CFG0 0x1214
  295. #define MT_BB_PA_MODE_CFG1 0x1218
  296. #define MT_RF_PA_MODE_CFG0 0x121c
  297. #define MT_RF_PA_MODE_CFG1 0x1220
  298. #define MT_RF_PA_MODE_ADJ0 0x1228
  299. #define MT_RF_PA_MODE_ADJ1 0x122c
  300. #define MT_DACCLK_EN_DLY_CFG 0x1264
  301. #define MT_EDCA_CFG_BASE 0x1300
  302. #define MT_EDCA_CFG_AC(_n) (MT_EDCA_CFG_BASE + ((_n) << 2))
  303. #define MT_EDCA_CFG_TXOP GENMASK(7, 0)
  304. #define MT_EDCA_CFG_AIFSN GENMASK(11, 8)
  305. #define MT_EDCA_CFG_CWMIN GENMASK(15, 12)
  306. #define MT_EDCA_CFG_CWMAX GENMASK(19, 16)
  307. #define MT_TX_PWR_CFG_0 0x1314
  308. #define MT_TX_PWR_CFG_1 0x1318
  309. #define MT_TX_PWR_CFG_2 0x131c
  310. #define MT_TX_PWR_CFG_3 0x1320
  311. #define MT_TX_PWR_CFG_4 0x1324
  312. #define MT_TX_PIN_CFG 0x1328
  313. #define MT_TX_PIN_CFG_TXANT GENMASK(3, 0)
  314. #define MT_TX_PIN_CFG_RXANT GENMASK(11, 8)
  315. #define MT_TX_PIN_RFTR_EN BIT(16)
  316. #define MT_TX_PIN_TRSW_EN BIT(18)
  317. #define MT_TX_BAND_CFG 0x132c
  318. #define MT_TX_BAND_CFG_UPPER_40M BIT(0)
  319. #define MT_TX_BAND_CFG_5G BIT(1)
  320. #define MT_TX_BAND_CFG_2G BIT(2)
  321. #define MT_HT_FBK_TO_LEGACY 0x1384
  322. #define MT_TX_MPDU_ADJ_INT 0x1388
  323. #define MT_TX_PWR_CFG_7 0x13d4
  324. #define MT_TX_PWR_CFG_8 0x13d8
  325. #define MT_TX_PWR_CFG_9 0x13dc
  326. #define MT_TX_SW_CFG0 0x1330
  327. #define MT_TX_SW_CFG1 0x1334
  328. #define MT_TX_SW_CFG2 0x1338
  329. #define MT_TXOP_CTRL_CFG 0x1340
  330. #define MT_TXOP_TRUN_EN GENMASK(5, 0)
  331. #define MT_TXOP_EXT_CCA_DLY GENMASK(15, 8)
  332. #define MT_TXOP_ED_CCA_EN BIT(20)
  333. #define MT_TX_RTS_CFG 0x1344
  334. #define MT_TX_RTS_CFG_RETRY_LIMIT GENMASK(7, 0)
  335. #define MT_TX_RTS_CFG_THRESH GENMASK(23, 8)
  336. #define MT_TX_RTS_FALLBACK BIT(24)
  337. #define MT_TX_TIMEOUT_CFG 0x1348
  338. #define MT_TX_TIMEOUT_CFG_ACKTO GENMASK(15, 8)
  339. #define MT_TX_RETRY_CFG 0x134c
  340. #define MT_TX_LINK_CFG 0x1350
  341. #define MT_TX_CFACK_EN BIT(12)
  342. #define MT_VHT_HT_FBK_CFG0 0x1354
  343. #define MT_VHT_HT_FBK_CFG1 0x1358
  344. #define MT_LG_FBK_CFG0 0x135c
  345. #define MT_LG_FBK_CFG1 0x1360
  346. #define MT_PROT_CFG_RATE GENMASK(15, 0)
  347. #define MT_PROT_CFG_CTRL GENMASK(17, 16)
  348. #define MT_PROT_CFG_NAV GENMASK(19, 18)
  349. #define MT_PROT_CFG_TXOP_ALLOW GENMASK(25, 20)
  350. #define MT_PROT_CFG_RTS_THRESH BIT(26)
  351. #define MT_CCK_PROT_CFG 0x1364
  352. #define MT_OFDM_PROT_CFG 0x1368
  353. #define MT_MM20_PROT_CFG 0x136c
  354. #define MT_MM40_PROT_CFG 0x1370
  355. #define MT_GF20_PROT_CFG 0x1374
  356. #define MT_GF40_PROT_CFG 0x1378
  357. #define MT_PROT_RATE GENMASK(15, 0)
  358. #define MT_PROT_CTRL_RTS_CTS BIT(16)
  359. #define MT_PROT_CTRL_CTS2SELF BIT(17)
  360. #define MT_PROT_NAV_SHORT BIT(18)
  361. #define MT_PROT_NAV_LONG BIT(19)
  362. #define MT_PROT_TXOP_ALLOW_CCK BIT(20)
  363. #define MT_PROT_TXOP_ALLOW_OFDM BIT(21)
  364. #define MT_PROT_TXOP_ALLOW_MM20 BIT(22)
  365. #define MT_PROT_TXOP_ALLOW_MM40 BIT(23)
  366. #define MT_PROT_TXOP_ALLOW_GF20 BIT(24)
  367. #define MT_PROT_TXOP_ALLOW_GF40 BIT(25)
  368. #define MT_PROT_RTS_THR_EN BIT(26)
  369. #define MT_PROT_RATE_CCK_11 0x0003
  370. #define MT_PROT_RATE_OFDM_6 0x2000
  371. #define MT_PROT_RATE_OFDM_24 0x2004
  372. #define MT_PROT_RATE_DUP_OFDM_24 0x2084
  373. #define MT_PROT_RATE_SGI_OFDM_24 0x2104
  374. #define MT_PROT_TXOP_ALLOW_ALL GENMASK(25, 20)
  375. #define MT_PROT_TXOP_ALLOW_BW20 (MT_PROT_TXOP_ALLOW_ALL & \
  376. ~MT_PROT_TXOP_ALLOW_MM40 & \
  377. ~MT_PROT_TXOP_ALLOW_GF40)
  378. #define MT_EXP_ACK_TIME 0x1380
  379. #define MT_TX_PWR_CFG_0_EXT 0x1390
  380. #define MT_TX_PWR_CFG_1_EXT 0x1394
  381. #define MT_TX_FBK_LIMIT 0x1398
  382. #define MT_TX_FBK_LIMIT_MPDU_FBK GENMASK(7, 0)
  383. #define MT_TX_FBK_LIMIT_AMPDU_FBK GENMASK(15, 8)
  384. #define MT_TX_FBK_LIMIT_MPDU_UP_CLEAR BIT(16)
  385. #define MT_TX_FBK_LIMIT_AMPDU_UP_CLEAR BIT(17)
  386. #define MT_TX_FBK_LIMIT_RATE_LUT BIT(18)
  387. #define MT_TX0_RF_GAIN_CORR 0x13a0
  388. #define MT_TX1_RF_GAIN_CORR 0x13a4
  389. #define MT_TX0_RF_GAIN_ATTEN 0x13a8
  390. #define MT_TX0_RF_GAIN_ATTEN 0x13a8 /* MT76x0 */
  391. #define MT_TX_ALC_CFG_0 0x13b0
  392. #define MT_TX_ALC_CFG_0_CH_INIT_0 GENMASK(5, 0)
  393. #define MT_TX_ALC_CFG_0_CH_INIT_1 GENMASK(13, 8)
  394. #define MT_TX_ALC_CFG_0_LIMIT_0 GENMASK(21, 16)
  395. #define MT_TX_ALC_CFG_0_LIMIT_1 GENMASK(29, 24)
  396. #define MT_TX_ALC_CFG_1 0x13b4
  397. #define MT_TX_ALC_CFG_1_TEMP_COMP GENMASK(5, 0)
  398. #define MT_TX_ALC_CFG_2 0x13a8
  399. #define MT_TX_ALC_CFG_2_TEMP_COMP GENMASK(5, 0)
  400. #define MT_TX_ALC_CFG_3 0x13ac
  401. #define MT_TX_ALC_CFG_4 0x13c0
  402. #define MT_TX_ALC_CFG_4_LOWGAIN_CH_EN BIT(31)
  403. #define MT_TX0_BB_GAIN_ATTEN 0x13c0 /* MT76x0 */
  404. #define MT_TX_ALC_VGA3 0x13c8
  405. #define MT_TX_PROT_CFG6 0x13e0
  406. #define MT_TX_PROT_CFG7 0x13e4
  407. #define MT_TX_PROT_CFG8 0x13e8
  408. #define MT_PIFS_TX_CFG 0x13ec
  409. #define MT_RX_FILTR_CFG 0x1400
  410. #define MT_RX_FILTR_CFG_CRC_ERR BIT(0)
  411. #define MT_RX_FILTR_CFG_PHY_ERR BIT(1)
  412. #define MT_RX_FILTR_CFG_PROMISC BIT(2)
  413. #define MT_RX_FILTR_CFG_OTHER_BSS BIT(3)
  414. #define MT_RX_FILTR_CFG_VER_ERR BIT(4)
  415. #define MT_RX_FILTR_CFG_MCAST BIT(5)
  416. #define MT_RX_FILTR_CFG_BCAST BIT(6)
  417. #define MT_RX_FILTR_CFG_DUP BIT(7)
  418. #define MT_RX_FILTR_CFG_CFACK BIT(8)
  419. #define MT_RX_FILTR_CFG_CFEND BIT(9)
  420. #define MT_RX_FILTR_CFG_ACK BIT(10)
  421. #define MT_RX_FILTR_CFG_CTS BIT(11)
  422. #define MT_RX_FILTR_CFG_RTS BIT(12)
  423. #define MT_RX_FILTR_CFG_PSPOLL BIT(13)
  424. #define MT_RX_FILTR_CFG_BA BIT(14)
  425. #define MT_RX_FILTR_CFG_BAR BIT(15)
  426. #define MT_RX_FILTR_CFG_CTRL_RSV BIT(16)
  427. #define MT_AUTO_RSP_CFG 0x1404
  428. #define MT_AUTO_RSP_EN BIT(0)
  429. #define MT_AUTO_RSP_PREAMB_SHORT BIT(4)
  430. #define MT_LEGACY_BASIC_RATE 0x1408
  431. #define MT_HT_BASIC_RATE 0x140c
  432. #define MT_HT_CTRL_CFG 0x1410
  433. #define MT_RX_PARSER_CFG 0x1418
  434. #define MT_RX_PARSER_RX_SET_NAV_ALL BIT(0)
  435. #define MT_EXT_CCA_CFG 0x141c
  436. #define MT_EXT_CCA_CFG_CCA0 GENMASK(1, 0)
  437. #define MT_EXT_CCA_CFG_CCA1 GENMASK(3, 2)
  438. #define MT_EXT_CCA_CFG_CCA2 GENMASK(5, 4)
  439. #define MT_EXT_CCA_CFG_CCA3 GENMASK(7, 6)
  440. #define MT_EXT_CCA_CFG_CCA_MASK GENMASK(11, 8)
  441. #define MT_EXT_CCA_CFG_ED_CCA_MASK GENMASK(15, 12)
  442. #define MT_TX_SW_CFG3 0x1478
  443. #define MT_PN_PAD_MODE 0x150c
  444. #define MT_TXOP_HLDR_ET 0x1608
  445. #define MT_TXOP_HLDR_TX40M_BLK_EN BIT(1)
  446. #define MT_PROT_AUTO_TX_CFG 0x1648
  447. #define MT_PROT_AUTO_TX_CFG_PROT_PADJ GENMASK(11, 8)
  448. #define MT_PROT_AUTO_TX_CFG_AUTO_PADJ GENMASK(27, 24)
  449. #define MT_RX_STAT_0 0x1700
  450. #define MT_RX_STAT_0_CRC_ERRORS GENMASK(15, 0)
  451. #define MT_RX_STAT_0_PHY_ERRORS GENMASK(31, 16)
  452. #define MT_RX_STAT_1 0x1704
  453. #define MT_RX_STAT_1_CCA_ERRORS GENMASK(15, 0)
  454. #define MT_RX_STAT_1_PLCP_ERRORS GENMASK(31, 16)
  455. #define MT_RX_STAT_2 0x1708
  456. #define MT_RX_STAT_2_DUP_ERRORS GENMASK(15, 0)
  457. #define MT_RX_STAT_2_OVERFLOW_ERRORS GENMASK(31, 16)
  458. #define MT_TX_STA_0 0x170c
  459. #define MT_TX_STA_1 0x1710
  460. #define MT_TX_STA_2 0x1714
  461. #define MT_TX_STAT_FIFO 0x1718
  462. #define MT_TX_STAT_FIFO_VALID BIT(0)
  463. #define MT_TX_STAT_FIFO_SUCCESS BIT(5)
  464. #define MT_TX_STAT_FIFO_AGGR BIT(6)
  465. #define MT_TX_STAT_FIFO_ACKREQ BIT(7)
  466. #define MT_TX_STAT_FIFO_WCID GENMASK(15, 8)
  467. #define MT_TX_STAT_FIFO_RATE GENMASK(31, 16)
  468. #define MT_TX_AGG_STAT 0x171c
  469. #define MT_TX_AGG_CNT_BASE0 0x1720
  470. #define MT_MPDU_DENSITY_CNT 0x1740
  471. #define MT_TX_AGG_CNT_BASE1 0x174c
  472. #define MT_TX_AGG_CNT(_id) ((_id) < 8 ? \
  473. MT_TX_AGG_CNT_BASE0 + ((_id) << 2) : \
  474. MT_TX_AGG_CNT_BASE1 + (((_id) - 8) << 2))
  475. #define MT_TX_STAT_FIFO_EXT 0x1798
  476. #define MT_TX_STAT_FIFO_EXT_RETRY GENMASK(7, 0)
  477. #define MT_TX_STAT_FIFO_EXT_PKTID GENMASK(15, 8)
  478. #define MT_WCID_TX_RATE_BASE 0x1c00
  479. #define MT_WCID_TX_RATE(_i) (MT_WCID_TX_RATE_BASE + ((_i) << 3))
  480. #define MT_BBP_CORE_BASE 0x2000
  481. #define MT_BBP_IBI_BASE 0x2100
  482. #define MT_BBP_AGC_BASE 0x2300
  483. #define MT_BBP_TXC_BASE 0x2400
  484. #define MT_BBP_RXC_BASE 0x2500
  485. #define MT_BBP_TXO_BASE 0x2600
  486. #define MT_BBP_TXBE_BASE 0x2700
  487. #define MT_BBP_RXFE_BASE 0x2800
  488. #define MT_BBP_RXO_BASE 0x2900
  489. #define MT_BBP_DFS_BASE 0x2a00
  490. #define MT_BBP_TR_BASE 0x2b00
  491. #define MT_BBP_CAL_BASE 0x2c00
  492. #define MT_BBP_DSC_BASE 0x2e00
  493. #define MT_BBP_PFMU_BASE 0x2f00
  494. #define MT_BBP(_type, _n) (MT_BBP_##_type##_BASE + ((_n) << 2))
  495. #define MT_BBP_CORE_R1_BW GENMASK(4, 3)
  496. #define MT_BBP_AGC_R0_CTRL_CHAN GENMASK(9, 8)
  497. #define MT_BBP_AGC_R0_BW GENMASK(14, 12)
  498. /* AGC, R4/R5 */
  499. #define MT_BBP_AGC_LNA_HIGH_GAIN GENMASK(21, 16)
  500. #define MT_BBP_AGC_LNA_MID_GAIN GENMASK(13, 8)
  501. #define MT_BBP_AGC_LNA_LOW_GAIN GENMASK(5, 0)
  502. /* AGC, R6/R7 */
  503. #define MT_BBP_AGC_LNA_ULOW_GAIN GENMASK(5, 0)
  504. /* AGC, R8/R9 */
  505. #define MT_BBP_AGC_LNA_GAIN_MODE GENMASK(7, 6)
  506. #define MT_BBP_AGC_GAIN GENMASK(14, 8)
  507. #define MT_BBP_AGC20_RSSI0 GENMASK(7, 0)
  508. #define MT_BBP_AGC20_RSSI1 GENMASK(15, 8)
  509. #define MT_BBP_TXBE_R0_CTRL_CHAN GENMASK(1, 0)
  510. #define MT_WCID_ADDR_BASE 0x1800
  511. #define MT_WCID_ADDR(_n) (MT_WCID_ADDR_BASE + (_n) * 8)
  512. #define MT_SRAM_BASE 0x4000
  513. #define MT_WCID_KEY_BASE 0x8000
  514. #define MT_WCID_KEY(_n) (MT_WCID_KEY_BASE + (_n) * 32)
  515. #define MT_WCID_IV_BASE 0xa000
  516. #define MT_WCID_IV(_n) (MT_WCID_IV_BASE + (_n) * 8)
  517. #define MT_WCID_ATTR_BASE 0xa800
  518. #define MT_WCID_ATTR(_n) (MT_WCID_ATTR_BASE + (_n) * 4)
  519. #define MT_WCID_ATTR_PAIRWISE BIT(0)
  520. #define MT_WCID_ATTR_PKEY_MODE GENMASK(3, 1)
  521. #define MT_WCID_ATTR_BSS_IDX GENMASK(6, 4)
  522. #define MT_WCID_ATTR_RXWI_UDF GENMASK(9, 7)
  523. #define MT_WCID_ATTR_PKEY_MODE_EXT BIT(10)
  524. #define MT_WCID_ATTR_BSS_IDX_EXT BIT(11)
  525. #define MT_WCID_ATTR_WAPI_MCBC BIT(15)
  526. #define MT_WCID_ATTR_WAPI_KEYID GENMASK(31, 24)
  527. #define MT_SKEY_BASE_0 0xac00
  528. #define MT_SKEY_BASE_1 0xb400
  529. #define MT_SKEY_0(_bss, _idx) (MT_SKEY_BASE_0 + (4 * (_bss) + (_idx)) * 32)
  530. #define MT_SKEY_1(_bss, _idx) (MT_SKEY_BASE_1 + (4 * ((_bss) & 7) + (_idx)) * 32)
  531. #define MT_SKEY(_bss, _idx) (((_bss) & 8) ? MT_SKEY_1(_bss, _idx) : MT_SKEY_0(_bss, _idx))
  532. #define MT_SKEY_MODE_BASE_0 0xb000
  533. #define MT_SKEY_MODE_BASE_1 0xb3f0
  534. #define MT_SKEY_MODE_0(_bss) (MT_SKEY_MODE_BASE_0 + (((_bss) / 2) << 2))
  535. #define MT_SKEY_MODE_1(_bss) (MT_SKEY_MODE_BASE_1 + ((((_bss) & 7) / 2) << 2))
  536. #define MT_SKEY_MODE(_bss) (((_bss) & 8) ? MT_SKEY_MODE_1(_bss) : MT_SKEY_MODE_0(_bss))
  537. #define MT_SKEY_MODE_MASK GENMASK(3, 0)
  538. #define MT_SKEY_MODE_SHIFT(_bss, _idx) (4 * ((_idx) + 4 * ((_bss) & 1)))
  539. #define MT_BEACON_BASE 0xc000
  540. #define MT_TEMP_SENSOR 0x1d000
  541. #define MT_TEMP_SENSOR_VAL GENMASK(6, 0)
  542. struct mt76_wcid_addr {
  543. u8 macaddr[6];
  544. __le16 ba_mask;
  545. } __packed __aligned(4);
  546. struct mt76_wcid_key {
  547. u8 key[16];
  548. u8 tx_mic[8];
  549. u8 rx_mic[8];
  550. } __packed __aligned(4);
  551. enum mt76x02_cipher_type {
  552. MT_CIPHER_NONE,
  553. MT_CIPHER_WEP40,
  554. MT_CIPHER_WEP104,
  555. MT_CIPHER_TKIP,
  556. MT_CIPHER_AES_CCMP,
  557. MT_CIPHER_CKIP40,
  558. MT_CIPHER_CKIP104,
  559. MT_CIPHER_CKIP128,
  560. MT_CIPHER_WAPI,
  561. };
  562. #endif